10Mhz out: from pll or from fpga ?
On the initial diagram, the 10Mhz out clock is generated from the clean-up pll. On the schematics, it comes from the fpga, so it won't be as clean as if it comes from the pll.
On the initial diagram, the 10Mhz out clock is generated from the clean-up pll. On the schematics, it comes from the fpga, so it won't be as clean as if it comes from the pll.