Questions about trigger units for previous designers
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start and stop are external and asynchronous. Need a sync circuit to clean them. What's the impact of additional latency?
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What is the delay between Start and Sync ?
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Check stop is external.
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What's the SyncPulse ?
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Do we need an asynchronous clk cleaning circuit on the RST. Does RST come from FESA?
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Reset handling.
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Clk - is the RF clock divided by 8 because of the sync input being put through an iserdes.
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SDR or DDR in the iserdes?
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Do we need x4 rf clock inputs for each trigger unit for both RF channels
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Where and what clock regions will be used...? One per RF channel
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How many IDELAYCTRL blocks will we need, one per region?
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How many BUFRs per iobank/clock region
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Can we bufg the RF clock and get div by 8 for the i/oserdes
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Could the second trigger unit use the same input as the first one ? Why are they chained ?
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Is any interlock generated ?