Page version | Author | Commit Message | Last updated | Format |
---|---|---|---|---|
87caf54c | Evangelia Gousiou | Added link to calibration page | markdown | |
92f1429c | Adam Wujek | add info about Gateware release v0.17 | markdown | |
299d64c7 | Evangelia Gousiou | corrected date of v0.16 release in the status table | markdown | |
8342725a | Evangelia Gousiou | Removed BOBR section; added link to v0.16 release in the project information; added v0.16 in the status table | markdown | |
10f32516 | John Gill | Latest updates | markdown | |
585c9ddc | Erik van der Bij | Typo Ethenet | markdown | |
669cf468 | John Gill | Stable RF and trigger units signals observed, relative to a nco_reset received over WR | markdown | |
34bde62e | Erik van der Bij | Status: |15-02-2021| V2 PCB layout ready. | | markdown | |
52eb723e | John Gill | First installation | markdown | |
4225209b | Erik van der Bij | Corrected edms link, pointing to top project so that can find V1 and V2 | markdown | |
08332d70 | Erik van der Bij | Updated link to EDMS | markdown | |
0ebd6757 | John Gill | Beta gateware released, update status | markdown | |
87249b34 | John Gill | Update home | markdown | |
b2bfff6f | Tristan Gingold | Add link to schema | markdown | |
df62a80c | Erik van der Bij | Status: |26-10-2020|PCB design ready. Production of prototypes can start. | | markdown | |
c0c0ec47 | Erik van der Bij | |20-10-2020|PCB design reviewed, corrections to be done by design office. | | markdown | |
ebbd9dbb | Erik van der Bij | Added FPGA type, status | markdown | |
d4436b6b | Dimitris Lampridis | Update status table | markdown | |
69c22138 | Dimitris Lampridis | fix typo | markdown | |
b51b719e | Dimitris Lampridis | Update status table | markdown |