WR2RF FPGA Clocking
This page provides an overview for the clocking architecture utilised on the FPGA.
Initialisation
The clock dmtd_clk is available on boot but the clock clk_fpga_sys_62m5 from the LTC6950 is not. To generate the low jitter clk_fpga_sys_62m5, first the LTC6950 must be programmed, along with other peripherals.
Therefore, for initialisation we utilise the dmtd_clk to provide a clock to initialise the peripherals and the clk_fpga_sys from the LTC6950. Once the clk_fpga_sys is available and stable, we switch the source of the FPGA's clk_sys to originate from the LTC6950. This is achieved using a BUFGCTRL cell.
FPGA clk_ref and clk_sys
There is no requirement for these clocks to originate from different sources. The clk_ref is used to clock logic in the FPGA fabric that drives data to and from the WR transceivers. Its frequency depends upon the PCS configuration and its pipe data width. Usually we end-up with one of two configurations:
- Pipewidth 8 bits implies the clk_ref frequency is 125 MHz
- Pipewidth 16 bits implies the clk_ref frequency is 62.5 MHz
On the WR2RF card we expect the pipewidth to be 16 bits and therefore the clk_ref will operate at 62.5 MHz.
For clk_sys, there need not be any difference in frequency between itself and clk_ref, so long as timing can be closed. For example, in some existing designs (e.g. SPEC) clk_ref operates at 125 MHz but the remaining logic cannot achieve timing closure at this frequency so clk_sys is generated from clk_ref using an on chip MMCM or PLL cell. In general, the frequency requirement for clk_sys is: clk_sys <= clk_ref.
FPGA Clock synthesis and distribution
We need a variety of clocks for the FPGA and BE-RF imported logic cores: RFNCO and IQModInterp2FIR. They are:
- clk 250 MHz
- clk 125 MHz
- clk 62.5 MHz
If we generate these clocks in the low jitter environment by sourcing a 250 MHz clock from the LTC6950. We can then use this clock to generate 125 MHz and 62.5 MHz frequencies using BUFGCE cells and decimating their outputs using the CE pins. This avoids using an MMCM for clk_sys frequency generation, thereby avoiding:
- additional noise being added to the system by the MMCM
- hold timing issues created by using an MMCM with internal clock feedback to minimise noise on the output clocks
Attached is a proposed clocking architecture (post implemention) illustrating the interplay between the clocks:
- clk_dmtd
- clk_sys_250m
- clk_sys_125m
- clk_sys_62m5
- clk_sys_200m - for IDELAYCTRL blocks to calibrate IDELAY and ODELAY cells.
Please note that for each clock there is a single BUFG or BUFGCTRL. This is super important to avoid differences in clock insertion to the root of each clock tree.