Considerations
This page is a working diary about the current ideas and issues for the implementation of WRAP.
Main idea
The main idea is to wrap all the WR PTP Core functionalities in a single
FPGA, offering time and data services.
Data services are provided by a flexibile data interface which can be
GMII or a simplified
interface
The image shows only one of the two SFP interfaces.
Simplified interface
The simplified interface uses the same lines of GMII to provide a simple interface from/to Ethernet. The interface behavior can be set through the management SPI of WRAP.
FPGA Package
The FPGA choice is of primary importance since its package affects the
compatibility of WRAP with newer version of WR PTP core.
Currently, the WR PTP Core has the following resource utilization, using
the default ram setting of WR PTP Core on a Artix
35T:
As you can see, the most scarce resource is the block ram, heavily used
by the LM32 inside the PTP Core.
I/O usage is about 80+ lines
- PTP core & timing: 41 I/O
- GMII + Management: 28
- Time services: 16+
Using two SFP requires two endpoints but not two LM32 cores, so the
block ram usage (BRAM) is not doubled.
Artix 35T has several package. Currently, two of them are under
evaluation:
- CSG325: 15mmx15mm BGA footprint (ball pitch 0.8mm)
- FGG484: 23mmx23mm BGA footpint (ball pitch 1mm)
Also CPG236 is available, but has a ball pitch of 0.5mm (PCB realization and soldering must be checked!)
CSG325
This package support up to 4 Gigabit Serdes. The footprint allow to
upgrade the WRAP board up to Artix 50T, which has 33% more BRAM.
General I/O lines: 106 (
FGG484
This package support up to 4 Gigabit Serdes. The footprint allow to upgrade the WRAP board up to Artix 100T, which has 250% more BRAM.
FMC Connector
- 2 differential clocks available (10 MHz and WR clock?)
- Additional 2 differential clocks for HPC connector (custom clock signal from PLL)
- 68 generic I/O
- 28 for Gigabit MII (single-ended, clock signals single-ended)
- PPS output, timecode output
- Time-services (timestamping & outputs) 20 (4 LVDS inputs, 2 single-ended inputs, 4 LVDS outputs, 2 single-ended outputs)
- About 15 I/O left for management and GPIO
Timing services
Timing services as timestamping of input events can be done using Serdes
of Artix. The generation of the required clock can be done using an
internal PLL or an external one (suggested solution). BUFG has a maximum
clock frequency near 500 MHz, BUFIO can be used to supply to the Serdes
a clock of 500MHz to achive 2ns resolution.
Retrieving of time-related services' data is done using a dedicated SPI.
Clocking scheme
The clocking scheme is very important. The goal is to achieve a phase
noise and jitter below the WR Switch.
Another key aspect is size, on a FMC form-factor the space is critical.
Oscillators
The DDMTD offset clock phase noise is not critical on the WR Switch
(check DDMTD report), so likely an external PLL to get the 62.5MHz
offset clock frequency is not needed. The suggestion is to check the
cleaniness of the internal PLLs of Artix-7 and use the approach
described in the DDMTD report to evaluate the effect on the phase
noise.
The Main VCTCXO suggested is DOT050F combined with an external PLL to
get the best phase noise.
The considered Main PLLs are:
- LTC6950
- LMK03806
LTC6950
The best solution for phase noise but it's rather expensive and require an external VCSO to get the best phase noise. Check space but likely cannot fit into FMC.
LMK03806
It has an internal VCO, so an higher phase noise at larger offset values (but still much better than the WR Switch) and is not as expensive as the LTC6950 solution (PLL+VCSO).
Custom clocks
Custom frequency clocks, which is any clock with a frequency different
than 62.5MHz (WR clock) are a big deal. The issue of providing a
deterministic clock rises from the divider uncertainity, since the PTP
daemon correctly align only the WR Clock. WR Switch solves the problem
using a Digital flip flop, which clean up a clock signal created using
the WR clock.
The clock cleaning solution provide extreme flexibility, but also a
phase noise at larger offset frequencies. The basic issue is that flip
flops output stages are not designed to carry high-quality clocks (but
data!).