Considerations
This page is a working diary about the current ideas and issues for the implementation of WRAP.
Main idea
The main idea is to wrap all the WR PTP Core functionalities in a single
FPGA, offering time and data services.
Data services are provided by a flexibile data interface which can be
GMII or a simplified interface
The simplified interface
FPGA Package
The FPGA choice is of primary importance since its package affects the
compatibility of WRAP with newer version of WR PTP core.
Currently, the WR PTP Core has the following resource utilization, using
the default ram setting of WR PTP Core on a Artix 35T