Considerations
This page is a working diary about the current ideas and issues for the implementation of WRAP.
Main idea
The main idea is to wrap all the WR PTP Core functionalities in a single
FPGA, offering time and data services.
Data services are provided by a flexibile data interface which can be
GMII or a simplified
interface
The image shows only one of the two SFP interfaces.
Simplified interface
The simplified interface uses the same lines of GMII to provide a simple interface from/to Ethernet. The interface behavior can be set through the management SPI of WRAP.
FPGA Package
The FPGA choice is of primary importance since its package affects the
compatibility of WRAP with newer version of WR PTP core.
Currently, the WR PTP Core has the following resource utilization, using
the default ram setting of WR PTP Core on a Artix
35T:
As you can see, the most scarce resource is the block ram, heavily used
by the LM32 inside the PTP Core.
I/O usage is about 80+ lines
- PTP core & timing: 41 I/O
- GMII + Management: 28
- Time services: 16+
Using two SFP requires two endpoints but not two LM32 cores, so the
block ram usage (BRAM) is not doubled.
Artix 35T has several package. Currently, two of them are under
evaluation:
- CSG325: 15mmx15mm BGA footprint (ball pitch 0.8mm)
- FGG484: 23mmx23mm BGA footpint (ball pitch 1mm)
Also CPG236 is available, but has a ball pitch of 0.5mm (PCB realization and soldering must be checked!)
CSG325
This package support up to 4 Gigabit Serdes. The footprint allow to
upgrade the WRAP board up to Artix 50T, which has 33% more BRAM.
General I/O lines: 106 (
FGG484
This package support up to 4 Gigabit Serdes. The footprint allow to upgrade the WRAP board up to Artix 100T, which has 250% more BRAM.