wrsw_sflow_wb Project Status (03/05/2012 - 11:54:10) | |||
Project File: | sflow.xise | Parser Errors: | |
Module Name: | wrsw_sflow_wb | Implementation State: | Translated (Failed) |
Target Device: | xc6vlx130t-1ff1156 |
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X 2 Errors (0 new) |
Product Version: | ISE 13.2 |
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64 Warnings (64 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 110 | 160000 | 0% | |
Number of Slice LUTs | 215 | 80000 | 0% | |
Number of fully used LUT-FF pairs | 108 | 217 | 49% | |
Number of bonded IOBs | 270 | 600 | 45% | |
Number of BUFG/BUFGCTRLs | 1 | 32 | 3% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mo. Mrz 5 11:52:59 2012 | 0 | 64 Warnings (64 new) | 32 Infos (32 new) | |
Translation Report | Current | Mo. Mrz 5 11:54:09 2012 | X 2 Errors (0 new) | 0 | 0 | |
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |