/*
  Register definitions for slave core: Generic Fine Pulse Generator Unit

  * File           : wb_fine_pulse_gen.h
  * Author         : auto-generated by wbgen2 from fine_pulse_gen_wb.wb
  * Created        : Wed Apr  8 15:49:26 2020
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fine_pulse_gen_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_FINE_PULSE_GEN_WB_WB
#define __WBGEN2_REGDEFS_FINE_PULSE_GEN_WB_WB

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Control/Status Register */

/* definitions for field: Trigger Sync Pulse 0 in reg: Control/Status Register */
#define FPG_CSR_TRIG0                         WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Trigger Sync Pulse 1 in reg: Control/Status Register */
#define FPG_CSR_TRIG1                         WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Trigger Sync Pulse 2 in reg: Control/Status Register */
#define FPG_CSR_TRIG2                         WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Trigger Sync Pulse 3 in reg: Control/Status Register */
#define FPG_CSR_TRIG3                         WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Trigger Sync Pulse 4 in reg: Control/Status Register */
#define FPG_CSR_TRIG4                         WBGEN2_GEN_MASK(4, 1)

/* definitions for field: Trigger Sync Pulse 5 in reg: Control/Status Register */
#define FPG_CSR_TRIG5                         WBGEN2_GEN_MASK(5, 1)

/* definitions for field: Trigger Sync Pulse 6 in reg: Control/Status Register */
#define FPG_CSR_TRIG6                         WBGEN2_GEN_MASK(6, 1)

/* definitions for field: Trigger Sync Pulse 7 in reg: Control/Status Register */
#define FPG_CSR_TRIG7                         WBGEN2_GEN_MASK(7, 1)

/* definitions for field: Immediately Force Sync Pulse 0 in reg: Control/Status Register */
#define FPG_CSR_FORCE0                        WBGEN2_GEN_MASK(8, 1)

/* definitions for field: Immediately Force Sync Pulse 1 in reg: Control/Status Register */
#define FPG_CSR_FORCE1                        WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Immediately Force Sync Pulse 2 in reg: Control/Status Register */
#define FPG_CSR_FORCE2                        WBGEN2_GEN_MASK(10, 1)

/* definitions for field: Immediately Force Sync Pulse 3 in reg: Control/Status Register */
#define FPG_CSR_FORCE3                        WBGEN2_GEN_MASK(11, 1)

/* definitions for field: Immediately Force Sync Pulse 4 in reg: Control/Status Register */
#define FPG_CSR_FORCE4                        WBGEN2_GEN_MASK(12, 1)

/* definitions for field: Immediately Force Sync Pulse 5 in reg: Control/Status Register */
#define FPG_CSR_FORCE5                        WBGEN2_GEN_MASK(13, 1)

/* definitions for field: Sync Pulse Ready in reg: Control/Status Register */
#define FPG_CSR_READY_MASK                    WBGEN2_GEN_MASK(14, 6)
#define FPG_CSR_READY_SHIFT                   14
#define FPG_CSR_READY_W(value)                WBGEN2_GEN_WRITE(value, 14, 6)
#define FPG_CSR_READY_R(reg)                  WBGEN2_GEN_READ(reg, 14, 6)

/* definitions for field: PLL Reset in reg: Control/Status Register */
#define FPG_CSR_PLL_RST                       WBGEN2_GEN_MASK(20, 1)

/* definitions for field: Serdes Reset in reg: Control/Status Register */
#define FPG_CSR_SERDES_RST                    WBGEN2_GEN_MASK(21, 1)

/* definitions for field: PLL Locked in reg: Control/Status Register */
#define FPG_CSR_PLL_LOCKED                    WBGEN2_GEN_MASK(22, 1)

/* definitions for register: Output 0 Control */

/* definitions for field: WR PPS offset in reg: Output 0 Control */
#define FPG_OCR0_PPS_OFFS_MASK                WBGEN2_GEN_MASK(0, 4)
#define FPG_OCR0_PPS_OFFS_SHIFT               0
#define FPG_OCR0_PPS_OFFS_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define FPG_OCR0_PPS_OFFS_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Fine delay adjust in reg: Output 0 Control */
#define FPG_OCR0_FINE_MASK                    WBGEN2_GEN_MASK(4, 5)
#define FPG_OCR0_FINE_SHIFT                   4
#define FPG_OCR0_FINE_W(value)                WBGEN2_GEN_WRITE(value, 4, 5)
#define FPG_OCR0_FINE_R(reg)                  WBGEN2_GEN_READ(reg, 4, 5)

/* definitions for field: Polarity in reg: Output 0 Control */
#define FPG_OCR0_POL                          WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Serdes Bitmask in reg: Output 0 Control */
#define FPG_OCR0_MASK_MASK                    WBGEN2_GEN_MASK(10, 8)
#define FPG_OCR0_MASK_SHIFT                   10
#define FPG_OCR0_MASK_W(value)                WBGEN2_GEN_WRITE(value, 10, 8)
#define FPG_OCR0_MASK_R(reg)                  WBGEN2_GEN_READ(reg, 10, 8)

/* definitions for field: Continuous mode select in reg: Output 0 Control */
#define FPG_OCR0_CONT                         WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Trigger select in reg: Output 0 Control */
#define FPG_OCR0_TRIG_SEL                     WBGEN2_GEN_MASK(19, 1)

/* definitions for register: Output 1 Control */

/* definitions for field: WR PPS offset in reg: Output 1 Control */
#define FPG_OCR1_PPS_OFFS_MASK                WBGEN2_GEN_MASK(0, 4)
#define FPG_OCR1_PPS_OFFS_SHIFT               0
#define FPG_OCR1_PPS_OFFS_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define FPG_OCR1_PPS_OFFS_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Fine delay adjust in reg: Output 1 Control */
#define FPG_OCR1_FINE_MASK                    WBGEN2_GEN_MASK(4, 5)
#define FPG_OCR1_FINE_SHIFT                   4
#define FPG_OCR1_FINE_W(value)                WBGEN2_GEN_WRITE(value, 4, 5)
#define FPG_OCR1_FINE_R(reg)                  WBGEN2_GEN_READ(reg, 4, 5)

/* definitions for field: Polarity in reg: Output 1 Control */
#define FPG_OCR1_POL                          WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Serdes Bitmask in reg: Output 1 Control */
#define FPG_OCR1_MASK_MASK                    WBGEN2_GEN_MASK(10, 8)
#define FPG_OCR1_MASK_SHIFT                   10
#define FPG_OCR1_MASK_W(value)                WBGEN2_GEN_WRITE(value, 10, 8)
#define FPG_OCR1_MASK_R(reg)                  WBGEN2_GEN_READ(reg, 10, 8)

/* definitions for field: Continuous mode select in reg: Output 1 Control */
#define FPG_OCR1_CONT                         WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Trigger select in reg: Output 1 Control */
#define FPG_OCR1_TRIG_SEL                     WBGEN2_GEN_MASK(19, 1)

/* definitions for register: Output 2 Control */

/* definitions for field: WR PPS offset in reg: Output 2 Control */
#define FPG_OCR2_PPS_OFFS_MASK                WBGEN2_GEN_MASK(0, 4)
#define FPG_OCR2_PPS_OFFS_SHIFT               0
#define FPG_OCR2_PPS_OFFS_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define FPG_OCR2_PPS_OFFS_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Fine delay adjust in reg: Output 2 Control */
#define FPG_OCR2_FINE_MASK                    WBGEN2_GEN_MASK(4, 5)
#define FPG_OCR2_FINE_SHIFT                   4
#define FPG_OCR2_FINE_W(value)                WBGEN2_GEN_WRITE(value, 4, 5)
#define FPG_OCR2_FINE_R(reg)                  WBGEN2_GEN_READ(reg, 4, 5)

/* definitions for field: Polarity in reg: Output 2 Control */
#define FPG_OCR2_POL                          WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Serdes Bitmask in reg: Output 2 Control */
#define FPG_OCR2_MASK_MASK                    WBGEN2_GEN_MASK(10, 8)
#define FPG_OCR2_MASK_SHIFT                   10
#define FPG_OCR2_MASK_W(value)                WBGEN2_GEN_WRITE(value, 10, 8)
#define FPG_OCR2_MASK_R(reg)                  WBGEN2_GEN_READ(reg, 10, 8)

/* definitions for field: Continuous mode select in reg: Output 2 Control */
#define FPG_OCR2_CONT                         WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Trigger select in reg: Output 2 Control */
#define FPG_OCR2_TRIG_SEL                     WBGEN2_GEN_MASK(19, 1)

/* definitions for register: Output 3 Control */

/* definitions for field: WR PPS offset in reg: Output 3 Control */
#define FPG_OCR3_PPS_OFFS_MASK                WBGEN2_GEN_MASK(0, 4)
#define FPG_OCR3_PPS_OFFS_SHIFT               0
#define FPG_OCR3_PPS_OFFS_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define FPG_OCR3_PPS_OFFS_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Fine delay adjust in reg: Output 3 Control */
#define FPG_OCR3_FINE_MASK                    WBGEN2_GEN_MASK(4, 5)
#define FPG_OCR3_FINE_SHIFT                   4
#define FPG_OCR3_FINE_W(value)                WBGEN2_GEN_WRITE(value, 4, 5)
#define FPG_OCR3_FINE_R(reg)                  WBGEN2_GEN_READ(reg, 4, 5)

/* definitions for field: Polarity in reg: Output 3 Control */
#define FPG_OCR3_POL                          WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Serdes Bitmask in reg: Output 3 Control */
#define FPG_OCR3_MASK_MASK                    WBGEN2_GEN_MASK(10, 8)
#define FPG_OCR3_MASK_SHIFT                   10
#define FPG_OCR3_MASK_W(value)                WBGEN2_GEN_WRITE(value, 10, 8)
#define FPG_OCR3_MASK_R(reg)                  WBGEN2_GEN_READ(reg, 10, 8)

/* definitions for field: Continuous mode select in reg: Output 3 Control */
#define FPG_OCR3_CONT                         WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Trigger select in reg: Output 3 Control */
#define FPG_OCR3_TRIG_SEL                     WBGEN2_GEN_MASK(19, 1)

/* definitions for register: Output 4 Control */

/* definitions for field: WR PPS offset in reg: Output 4 Control */
#define FPG_OCR4_PPS_OFFS_MASK                WBGEN2_GEN_MASK(0, 4)
#define FPG_OCR4_PPS_OFFS_SHIFT               0
#define FPG_OCR4_PPS_OFFS_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define FPG_OCR4_PPS_OFFS_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Fine delay adjust in reg: Output 4 Control */
#define FPG_OCR4_FINE_MASK                    WBGEN2_GEN_MASK(4, 5)
#define FPG_OCR4_FINE_SHIFT                   4
#define FPG_OCR4_FINE_W(value)                WBGEN2_GEN_WRITE(value, 4, 5)
#define FPG_OCR4_FINE_R(reg)                  WBGEN2_GEN_READ(reg, 4, 5)

/* definitions for field: Polarity in reg: Output 4 Control */
#define FPG_OCR4_POL                          WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Serdes Bitmask in reg: Output 4 Control */
#define FPG_OCR4_MASK_MASK                    WBGEN2_GEN_MASK(10, 8)
#define FPG_OCR4_MASK_SHIFT                   10
#define FPG_OCR4_MASK_W(value)                WBGEN2_GEN_WRITE(value, 10, 8)
#define FPG_OCR4_MASK_R(reg)                  WBGEN2_GEN_READ(reg, 10, 8)

/* definitions for field: Continuous mode select in reg: Output 4 Control */
#define FPG_OCR4_CONT                         WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Trigger select in reg: Output 4 Control */
#define FPG_OCR4_TRIG_SEL                     WBGEN2_GEN_MASK(19, 1)

/* definitions for register: Output 5 Control */

/* definitions for field: WR PPS offset in reg: Output 5 Control */
#define FPG_OCR5_PPS_OFFS_MASK                WBGEN2_GEN_MASK(0, 4)
#define FPG_OCR5_PPS_OFFS_SHIFT               0
#define FPG_OCR5_PPS_OFFS_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define FPG_OCR5_PPS_OFFS_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Fine delay adjust in reg: Output 5 Control */
#define FPG_OCR5_FINE_MASK                    WBGEN2_GEN_MASK(4, 5)
#define FPG_OCR5_FINE_SHIFT                   4
#define FPG_OCR5_FINE_W(value)                WBGEN2_GEN_WRITE(value, 4, 5)
#define FPG_OCR5_FINE_R(reg)                  WBGEN2_GEN_READ(reg, 4, 5)

/* definitions for field: Polarity in reg: Output 5 Control */
#define FPG_OCR5_POL                          WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Serdes Bitmask in reg: Output 5 Control */
#define FPG_OCR5_MASK_MASK                    WBGEN2_GEN_MASK(10, 8)
#define FPG_OCR5_MASK_SHIFT                   10
#define FPG_OCR5_MASK_W(value)                WBGEN2_GEN_WRITE(value, 10, 8)
#define FPG_OCR5_MASK_R(reg)                  WBGEN2_GEN_READ(reg, 10, 8)

/* definitions for field: Continuous mode select in reg: Output 5 Control */
#define FPG_OCR5_CONT                         WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Trigger select in reg: Output 5 Control */
#define FPG_OCR5_TRIG_SEL                     WBGEN2_GEN_MASK(19, 1)

/* definitions for register: Output 6 Control */

/* definitions for field: WR PPS offset in reg: Output 6 Control */
#define FPG_OCR6_PPS_OFFS_MASK                WBGEN2_GEN_MASK(0, 4)
#define FPG_OCR6_PPS_OFFS_SHIFT               0
#define FPG_OCR6_PPS_OFFS_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define FPG_OCR6_PPS_OFFS_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Fine delay adjust in reg: Output 6 Control */
#define FPG_OCR6_FINE_MASK                    WBGEN2_GEN_MASK(4, 5)
#define FPG_OCR6_FINE_SHIFT                   4
#define FPG_OCR6_FINE_W(value)                WBGEN2_GEN_WRITE(value, 4, 5)
#define FPG_OCR6_FINE_R(reg)                  WBGEN2_GEN_READ(reg, 4, 5)

/* definitions for field: Polarity in reg: Output 6 Control */
#define FPG_OCR6_POL                          WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Serdes Bitmask in reg: Output 6 Control */
#define FPG_OCR6_MASK_MASK                    WBGEN2_GEN_MASK(10, 8)
#define FPG_OCR6_MASK_SHIFT                   10
#define FPG_OCR6_MASK_W(value)                WBGEN2_GEN_WRITE(value, 10, 8)
#define FPG_OCR6_MASK_R(reg)                  WBGEN2_GEN_READ(reg, 10, 8)

/* definitions for field: Continuous mode select in reg: Output 6 Control */
#define FPG_OCR6_CONT                         WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Trigger select in reg: Output 6 Control */
#define FPG_OCR6_TRIG_SEL                     WBGEN2_GEN_MASK(19, 1)

/* definitions for register: Output 7 Control */

/* definitions for field: WR PPS offset in reg: Output 7 Control */
#define FPG_OCR7_PPS_OFFS_MASK                WBGEN2_GEN_MASK(0, 4)
#define FPG_OCR7_PPS_OFFS_SHIFT               0
#define FPG_OCR7_PPS_OFFS_W(value)            WBGEN2_GEN_WRITE(value, 0, 4)
#define FPG_OCR7_PPS_OFFS_R(reg)              WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for field: Fine delay adjust in reg: Output 7 Control */
#define FPG_OCR7_FINE_MASK                    WBGEN2_GEN_MASK(4, 5)
#define FPG_OCR7_FINE_SHIFT                   4
#define FPG_OCR7_FINE_W(value)                WBGEN2_GEN_WRITE(value, 4, 5)
#define FPG_OCR7_FINE_R(reg)                  WBGEN2_GEN_READ(reg, 4, 5)

/* definitions for field: Polarity in reg: Output 7 Control */
#define FPG_OCR7_POL                          WBGEN2_GEN_MASK(9, 1)

/* definitions for field: Serdes Bitmask in reg: Output 7 Control */
#define FPG_OCR7_MASK_MASK                    WBGEN2_GEN_MASK(10, 8)
#define FPG_OCR7_MASK_SHIFT                   10
#define FPG_OCR7_MASK_W(value)                WBGEN2_GEN_WRITE(value, 10, 8)
#define FPG_OCR7_MASK_R(reg)                  WBGEN2_GEN_READ(reg, 10, 8)

/* definitions for field: Continuous mode select in reg: Output 7 Control */
#define FPG_OCR7_CONT                         WBGEN2_GEN_MASK(18, 1)

/* definitions for field: Trigger select in reg: Output 7 Control */
#define FPG_OCR7_TRIG_SEL                     WBGEN2_GEN_MASK(19, 1)

/* definitions for register: Output Delay Calibration (Ultrascale-specific) */

/* definitions for field: Reset Output IDELAYCTRL in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_RST_IDELAYCTRL       WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Reset Output ODELAY in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_RST_ODELAY           WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Reset Output OSERDES in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_RST_OSERDES          WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Output Delay Ready in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_RDY                  WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Output Delay Value in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_VALUE_MASK           WBGEN2_GEN_MASK(4, 9)
#define FPG_ODELAY_CALIB_VALUE_SHIFT          4
#define FPG_ODELAY_CALIB_VALUE_W(value)       WBGEN2_GEN_WRITE(value, 4, 9)
#define FPG_ODELAY_CALIB_VALUE_R(reg)         WBGEN2_GEN_READ(reg, 4, 9)

/* definitions for field: Delay value update in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_VALUE_UPDATE         WBGEN2_GEN_MASK(13, 1)

/* definitions for field: Serdes Bitslip in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_BITSLIP_MASK         WBGEN2_GEN_MASK(14, 2)
#define FPG_ODELAY_CALIB_BITSLIP_SHIFT        14
#define FPG_ODELAY_CALIB_BITSLIP_W(value)     WBGEN2_GEN_WRITE(value, 14, 2)
#define FPG_ODELAY_CALIB_BITSLIP_R(reg)       WBGEN2_GEN_READ(reg, 14, 2)

/* definitions for field: Enable VT compensation in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_EN_VTC               WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Latch calibration taps in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_CAL_LATCH            WBGEN2_GEN_MASK(17, 1)

/* definitions for field: n Taps in reg: Output Delay Calibration (Ultrascale-specific) */
#define FPG_ODELAY_CALIB_TAPS_MASK            WBGEN2_GEN_MASK(18, 9)
#define FPG_ODELAY_CALIB_TAPS_SHIFT           18
#define FPG_ODELAY_CALIB_TAPS_W(value)        WBGEN2_GEN_WRITE(value, 18, 9)
#define FPG_ODELAY_CALIB_TAPS_R(reg)          WBGEN2_GEN_READ(reg, 18, 9)
/* [0x0]: REG Control/Status Register */
#define FPG_REG_CSR 0x00000000
/* [0x4]: REG Output 0 Control */
#define FPG_REG_OCR0 0x00000004
/* [0x8]: REG Output 1 Control */
#define FPG_REG_OCR1 0x00000008
/* [0xc]: REG Output 2 Control */
#define FPG_REG_OCR2 0x0000000c
/* [0x10]: REG Output 3 Control */
#define FPG_REG_OCR3 0x00000010
/* [0x14]: REG Output 4 Control */
#define FPG_REG_OCR4 0x00000014
/* [0x18]: REG Output 5 Control */
#define FPG_REG_OCR5 0x00000018
/* [0x1c]: REG Output 6 Control */
#define FPG_REG_OCR6 0x0000001c
/* [0x20]: REG Output 7 Control */
#define FPG_REG_OCR7 0x00000020
/* [0x24]: REG Output Delay Calibration (Ultrascale-specific) */
#define FPG_REG_ODELAY_CALIB 0x00000024
#endif
