\subsection{WR PTP Core component}
\label{sec:hdl_wrpc}
This section describes the input and output ports of the WRPC IP-core and VHDL generic parameters
that can be used to personalize the core.

The top-level VHDL module is located under:\\\hrefwrpc{modules/wrc\_core/wr\_core.vhd}

A wrapper for the top-level VHDL module which makes use of VHDL records to reduce the number of
ports can be found under:\\\hrefwrpc{modules/wrc\_core/xwr\_core.vhd}

\begin{figure}
  \begin{center}
    \includegraphics[width=.9\textheight, angle=270]{fig/basic_top.pdf}
    \caption{Simple top design with WRPC}
    \label{intro:fig:wrpc_top}
  \end{center}
\end{figure}

Figure \ref{intro:fig:wrpc_top} is an example on how to instantiate the WRPC component inside a
Xilinx Spartan6-based project. It contains few additional modules besides the WRPC:
\begin{itemize}
  \item \emph{wr\_gtp\_phy\_spartan6}: module wrapping Xilinx GTP SerDes to improve its determinism
  \item \emph{PLL\_BASE}: Xilinx Spartan6 PLL primitive \cite{pll_base}, used to produce 62.5 MHz
    system clock from 125 MHz local reference clock and to produce the DMTD offset clock from a
    local 20 MHz oscillator
  \item \emph{spec\_serial\_dac\_arb}: converts DACs tuning values to serial interface and
    arbitrates access to two DACs used for reference and DMTD clock tuning.
\end{itemize}

A very similar example can be found in the WRPC reference design for PCI-Express SPEC board (see
Section~\ref{sec:hdl_board_spec}).


\input{HDLdoc/wrc_generics.tex}
\input{HDLdoc/wrc_ports.tex}
\input{HDLdoc/phyif.tex}
\input{HDLdoc/periph.tex}
\input{HDLdoc/wb.tex}
\input{HDLdoc/fabric.tex}
\input{HDLdoc/txts.tex}
\input{HDLdoc/aux_clocks.tex}
\input{HDLdoc/timecode.tex}
\input{HDLdoc/aux_diag.tex}
