\subsubsection{Generic parameters}
\label{sec:wrc_generics}

\begin{hdlparamtable}
  g\_simulation & integer & 0 & setting to '1' speeds up the simulation,
  must be set to '0' for synthesis\\
  \hline
  g\_with\_external\_clock\_input & boolean & false &
  enable external clock and 1-PPS inputs. The PLL inside WRPC will lock to
  external 10 MHz and 1-PPS signal when operating in GrandMaster mode\\
  g\_phys\_uart & boolean & true & enable physical UART interface\\
  \hline
  g\_virtual\_uart & boolean & false & enable virtual UART interface\\
  \hline
  g\_aux\_clks & integer & 0 & number of aux clocks syntonized by WRPC to WR timebase\\
  \hline
  g\_rx\_buffer\_size & integer & 1024 & size of Rx buffer in WRPC MAC module,
  default value is 1024 and should not be changed\\
  \hline
  g\_tx\_runt\_padding & boolean & true & when set to true, all user frames
  transmitted from the external fabric interface are padded if shorter than
  minimal Ethernet frame size (60B with header)\\
  \hline
  g\_dpram\_initf & string & "" & filename of compiled WRPC software, to be
  stored in WRPC memory during the synthesis (default is \emph{wrc.ram}
  created by compiling WRPC software from \emph{wrpc-sw} git repository)\\
  \hline
  g\_dpram\_size & integer & 32768 & size of RAM used by WRPC software (in 32-bit
  words), default value is 22528 and should not be changed\\
  \hline
  g\_interface\_mode & enum& PIPELINED & external Wishbone Slave interface mode
  \tts{[PIPELINED/CLASSIC]}\\
  \hline
  g\_address\_granularity & enum & BYTE & granularity of address bus in external
  Wishbone Slave interface \tts{[BYTE/WORD]}\\
  \hline
  g\_aux\_sdb & rec & c\_wrc\_periph3\_sdb & structure providing an SDB descriptor
  for the peripheral attached to the WRPC auxiliary WB interface. This parameter is optional
  and can be left unassigned. The default value corresponds to an undocumented device with an
  address space of 256 bytes\\
  \hline
  g\_softpll\_enable\_debugger & boolean & false & when set to true, additional
  FIFO is instantiated in the SoftPLL for collecting DMTD tags. It can be read
  out by the host and analyzed for SoftPLL debugging.\\
  \hline
  g\_vuart\_fifo\_size & integer & 1024 & size (in bytes) for the virtual UART FIFO\\
  \hline
  g\_pcs\_16bit & boolean & false & when set to \tts{true}, make use of 16-bit PCS, otherwise use 8-bit PCS\\
  \hline
  g\_records\_for\_phy & boolean & false & when set to \tts{true}, all the PHY-related
  signals will be grouped in the \tts{phy8/phy16} VHDL records, otherwise the individual standard
  logic signals will be used\\
  \hline
  g\_diag\_id  & integer & 0 & auxiliary diagnostics module ID\\
  \hline
  g\_diag\_ver & integer  & 0 & auxiliary diagnostics version for a given module ID\\
  \hline
  g\_diag\_ro\_size & integer & 0 & number of read-only registers fed to auxiliary diagnostics\\
  \hline
  g\_diag\_rw\_size & integer & 0 & number of read-write registers fed to
  auxiliary diagnostics\\  
\end{hdlparamtable}
