Commit 3e4f8d1e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk

rt_cpu: disable PLL verbose mode by default (output on UART is blocking and…

rt_cpu: disable PLL verbose mode by default (output on UART is blocking and greatly slows down LDPC port calibration in the WR Switch)
parent 024b4964
......@@ -36,9 +36,9 @@ config TEMP_HIGH_THRESHOLD
config TEMP_HIGH_RAPPEL
int
default 60
config PLL_VERBOSE
boolean
default y if WR_SWITCH
config PFILTER_VERBOSE
boolean
......@@ -511,8 +511,7 @@ config PLL_VERBOSE
depends on DEVELOPER
boolean "Verbose messages in softpll"
help
The softpll is usually silent in WR node and verbose in WR
switch. You can enable pll messages in WR node for debugging.
Outputs additional debugging messages in the softpll. Off by default.
config PFILTER_VERBOSE
depends on DEVELOPER
......
......@@ -10,8 +10,8 @@ CONFIG_RAMSIZE=65536
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
CONFIG_PLL_VERBOSE=y
CONFIG_WRC_VERBOSE=y
CONFIG_PLL_VERBOSE=n
CONFIG_WRC_VERBOSE=n
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
......
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