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Software for White Rabbit PTP Core
Commits
3fbbe7b9
Commit
3fbbe7b9
authored
Feb 27, 2017
by
Adam Wujek
💬
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Merge branch "dlamprid-spll"
parents
4d261ef8
72c8d2a8
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6 changed files
with
28 additions
and
108 deletions
+28
-108
pps_gen.c
dev/pps_gen.c
+12
-0
pps_gen_regs.h
include/hw/pps_gen_regs.h
+12
-5
softpll_regs.h
include/hw/softpll_regs.h
+0
-0
pps_gen.h
include/pps_gen.h
+3
-0
ppsi
ppsi
+1
-1
pps_gen_regs.h
softpll/hw/pps_gen_regs.h
+0
-102
No files found.
dev/pps_gen.c
View file @
3fbbe7b9
...
...
@@ -134,3 +134,15 @@ int shw_pps_gen_enable_output(int enable)
return
0
;
}
/* Masks/unmasks PPS output when link is down (useful in master mode) */
int
shw_pps_gen_unmask_output
(
int
unmask
)
{
uint32_t
escr
=
ppsg_read
(
ESCR
);
if
(
unmask
)
ppsg_write
(
ESCR
,
escr
|
PPSG_ESCR_PPS_UNMASK
);
else
ppsg_write
(
ESCR
,
escr
&
~
PPSG_ESCR_PPS_UNMASK
);
return
0
;
}
include/hw/pps_gen_regs.h
View file @
3fbbe7b9
...
...
@@ -3,7 +3,7 @@
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Fri
Jul 26 15:09:09 2013
* Created : Fri
Feb 10 10:53:05 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
...
...
@@ -14,7 +14,11 @@
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
...
...
@@ -68,17 +72,20 @@
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS unmask output in reg: External sync control register */
#define PPSG_ESCR_PPS_UNMASK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(
1
, 1)
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(
2
, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(
2
, 1)
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(
3
, 1)
/* definitions for field: Set seconds counter in reg: External sync control register */
#define PPSG_ESCR_SEC_SET WBGEN2_GEN_MASK(
3
, 1)
#define PPSG_ESCR_SEC_SET WBGEN2_GEN_MASK(
4
, 1)
/* definitions for field: Set nanoseconds counter in reg: External sync control register */
#define PPSG_ESCR_NSEC_SET WBGEN2_GEN_MASK(
4
, 1)
#define PPSG_ESCR_NSEC_SET WBGEN2_GEN_MASK(
5
, 1)
PACKED
struct
PPSG_WB
{
/* [0x0]: REG Control Register */
...
...
softpll
/hw/softpll_regs.h
→
include
/hw/softpll_regs.h
View file @
3fbbe7b9
File moved
include/pps_gen.h
View file @
3fbbe7b9
...
...
@@ -26,6 +26,9 @@ int shw_pps_gen_busy(void);
/* Enables/disables PPS Generator PPS output */
int
shw_pps_gen_enable_output
(
int
enable
);
/* Masks/unmasks PPS output when link is down (useful in master mode) */
int
shw_pps_gen_unmask_output
(
int
unmask
);
/* Reads the current time and stores at <seconds,nanoseconds>. */
void
shw_pps_gen_get_time
(
uint64_t
*
seconds
,
uint32_t
*
nanoseconds
);
...
...
ppsi
@
d6aefd73
Subproject commit
f8cf1be371150883d1d3c9ba1a87b35b4e2b9f69
Subproject commit
d6aefd732b984cc4237277938ea183a038b53603
softpll/hw/pps_gen_regs.h
deleted
100644 → 0
View file @
4d261ef8
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created : Fri Jul 26 15:09:09 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Reset counter in reg: Control Register */
#define PPSG_CR_CNT_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable counter in reg: Control Register */
#define PPSG_CR_CNT_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Adjust offset in reg: Control Register */
#define PPSG_CR_CNT_ADJ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Set time in reg: Control Register */
#define PPSG_CR_CNT_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: PPS Pulse width in reg: Control Register */
#define PPSG_CR_PWIDTH_MASK WBGEN2_GEN_MASK(4, 28)
#define PPSG_CR_PWIDTH_SHIFT 4
#define PPSG_CR_PWIDTH_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define PPSG_CR_PWIDTH_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Nanosecond counter register */
/* definitions for register: UTC Counter register (least-significant part) */
/* definitions for register: UTC Counter register (most-significant part) */
/* definitions for register: Nanosecond adjustment register */
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Set seconds counter in reg: External sync control register */
#define PPSG_ESCR_SEC_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Set nanoseconds counter in reg: External sync control register */
#define PPSG_ESCR_NSEC_SET WBGEN2_GEN_MASK(4, 1)
PACKED
struct
PPSG_WB
{
/* [0x0]: REG Control Register */
uint32_t
CR
;
/* [0x4]: REG Nanosecond counter register */
uint32_t
CNTR_NSEC
;
/* [0x8]: REG UTC Counter register (least-significant part) */
uint32_t
CNTR_UTCLO
;
/* [0xc]: REG UTC Counter register (most-significant part) */
uint32_t
CNTR_UTCHI
;
/* [0x10]: REG Nanosecond adjustment register */
uint32_t
ADJ_NSEC
;
/* [0x14]: REG UTC Adjustment register (least-significant part) */
uint32_t
ADJ_UTCLO
;
/* [0x18]: REG UTC Adjustment register (most-significant part) */
uint32_t
ADJ_UTCHI
;
/* [0x1c]: REG External sync control register */
uint32_t
ESCR
;
};
#endif
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