Commit 46d036c8 authored by li hongming's avatar li hongming

update include/hw/wrc_syscon_regs.h

parent 8604cb0c
......@@ -28,7 +28,7 @@ char sfp_pn[wr_num_ports][SFP_PN_LEN];
int sfp_present(int port)
{
return (port) ? (!gpio_in(GPIO_DP_SFP_DET)) : (!gpio_in(GPIO_SFP_DET));
return (port) ? (!gpio_in(GPIO_SFP1_DET)) : (!gpio_in(GPIO_SFP_DET));
}
static int sfp_read_part_id(char *part_id, int port)
......
......@@ -13,7 +13,7 @@
struct s_i2c_if i2c_if[3] = {
{SYSC_GPSR_FMC_SCL, SYSC_GPSR_FMC_SDA, FMC_I2C_DELAY},
{SYSC_GPSR_SFP_SCL, SYSC_GPSR_SFP_SDA, SFP_I2C_DELAY},
{SYSC_GPSR_DP_SFP_SCL, SYSC_GPSR_DP_SFP_SDA, SFP_I2C_DELAY},
{SYSC_GPSR_SFP1_SCL, SYSC_GPSR_SFP1_SDA, SFP_I2C_DELAY},
};
volatile struct SYSCON_WB *syscon;
......@@ -136,14 +136,6 @@ void net_rst(void)
syscon->GPSR |= SYSC_GPSR_NET_RST;
}
void minic_rst(int port)
{
if (port==0)
syscon->GPSR |= SYSC_GPSR_MINIC_RST;
else
syscon->GPSR |= SYSC_GPSR_MINIC_DP_RST;
}
int wdiag_set_valid(int enable)
{
if (enable)
......
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Thu Nov 22 14:21:08 2018
* Created : Tue Jan 22 16:51:52 2019
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -90,26 +90,14 @@
/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MISO WBGEN2_GEN_MASK(13, 1)
/* definitions for field: DP Status LED in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_DP_LED_STAT WBGEN2_GEN_MASK(14, 1)
/* definitions for field: SFP1 detect (MOD_DEF0 signal) in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_DET WBGEN2_GEN_MASK(16, 1)
/* definitions for field: DP Link LED in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_DP_LED_LINK WBGEN2_GEN_MASK(15, 1)
/* definitions for field: SFP1 I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_SCL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: DP SFP detect (MOD_DEF0 signal) in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_DP_SFP_DET WBGEN2_GEN_MASK(16, 1)
/* definitions for field: DP SFP I2C bitbanged SCL in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_DP_SFP_SCL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: DP SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_DP_SFP_SDA WBGEN2_GEN_MASK(18, 1)
/* definitions for field: Minic reset in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_MINIC_RST WBGEN2_GEN_MASK(19, 1)
/* definitions for field: Minic DP reset in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_MINIC_DP_RST WBGEN2_GEN_MASK(20, 1)
/* definitions for field: SFP1 I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP1_SDA WBGEN2_GEN_MASK(18, 1)
/* definitions for register: GPIO Clear Register */
......@@ -140,17 +128,11 @@
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
/* definitions for field: DP Status LED in reg: GPIO Clear Register */
#define SYSC_GPCR_DP_LED_STAT WBGEN2_GEN_MASK(14, 1)
/* definitions for field: DP Link LED in reg: GPIO Clear Register */
#define SYSC_GPCR_DP_LED_LINK WBGEN2_GEN_MASK(15, 1)
/* definitions for field: DP SFP I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_DP_SFP_SCL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: SFP1 I2C bitbanged SCL in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP1_SCL WBGEN2_GEN_MASK(17, 1)
/* definitions for field: DP SFP I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_DP_SFP_SDA WBGEN2_GEN_MASK(18, 1)
/* definitions for field: SFP1 I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP1_SDA WBGEN2_GEN_MASK(18, 1)
/* definitions for register: Hardware Feature Register */
......
......@@ -81,12 +81,10 @@ struct SYSCON_WB {
/*GPIO pins*/
#define GPIO_LED_LINK SYSC_GPSR_LED_LINK
#define GPIO_LED_STAT SYSC_GPSR_LED_STAT
#define GPIO_DP_LED_LINK SYSC_GPSR_DP_LED_LINK
#define GPIO_DP_LED_STAT SYSC_GPSR_DP_LED_STAT
#define GPIO_BTN1 SYSC_GPSR_BTN1
#define GPIO_BTN2 SYSC_GPSR_BTN2
#define GPIO_SFP_DET SYSC_GPSR_SFP_DET
#define GPIO_DP_SFP_DET SYSC_GPSR_DP_SFP_DET
#define GPIO_SFP1_DET SYSC_GPSR_SFP1_DET
#define GPIO_SPI_SCLK SYSC_GPSR_SPI_SCLK
#define GPIO_SPI_NCS SYSC_GPSR_SPI_NCS
#define GPIO_SPI_MOSI SYSC_GPSR_SPI_MOSI
......@@ -144,7 +142,6 @@ int diag_read_word(uint32_t adr, int bank, uint32_t *val);
int diag_write_word(uint32_t adr, uint32_t val);
void net_rst(void);
void minic_rst(int port);
int wdiag_set_valid(int enable);
int wdiag_get_valid(void);
......
......@@ -102,8 +102,6 @@ static void wrc_initialize(void)
//Duplicate the configuration for both ports.
for (port=0; port<wr_num_ports;port++)
{
minic_rst(port);
pp_printf("PORT %d Local MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n", port,
mac_addr[port][0], mac_addr[port][1], mac_addr[port][2], mac_addr[port][3],
mac_addr[port][4], mac_addr[port][5]);
......@@ -170,7 +168,6 @@ static int wrc_check_link(void)
if (!prev_state[port] && state[port]) {
wrc_verbose("Port 0 Link up.\n");
if (port==0) gpio_out(GPIO_LED_LINK, 1);
else gpio_out(GPIO_DP_LED_LINK, 1);
sfp_match(port);
calib_t24p(WRC_MODE_MASTER, &cal_phase_transition[port],port);
wrc_ptp_start(port);
......@@ -179,10 +176,8 @@ static int wrc_check_link(void)
} else if (prev_state[port] && !state[port]) {
wrc_verbose("Port %d Link down.\n",port);
if (port==0) gpio_out(GPIO_LED_LINK, 0);
else gpio_out(GPIO_DP_LED_LINK, 0);
link_status[port] = LINK_WENT_DOWN;
wrc_ptp_stop(port);
minic_rst(port);
timer_delay_ms(1);
minic_init(port);
/* special case */
......
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