Merge branch 'greg-doc' into proposed_master

57c9ea17 · Grzegorz Daniluk · b5d556de · 2d4d4313 · 57c9ea17 · 57c9ea17
Commit 57c9ea17 authored Jul 04, 2017 by Grzegorz Daniluk
5 changed files
--- a/doc/HDLdoc/wrc_board.tex
+++ b/doc/HDLdoc/wrc_board.tex
@@ -116,7 +116,7 @@ their own BSP, can find the board-common module under:
  rst\_62m5\_n\_o & out & 1 & Active low reset output, synchronous to \tts{clk\_sys\_62m5\_o}\\
  \hline
  rst\_125m\_n\_o & out & 1 & Active low reset output, synchronous to \tts{clk\_ref\_125m\_o}\\
-  \hline\pagebreak
+  \hline
  \hdltablesection{Interface with SFP}\\
  \hline
  sfp\_tx\_fault\_i & in & 1 & TX fault indicator\\
@@ -222,7 +222,7 @@ their own BSP, can find the board-common module under:
  \hline
  tm\_clk\_aux\_locked\_o & out & var & auxiliary clock locked to internal WR
  clock. Size is equal to \tts{g\_aux\_clks}\\
-  \hline  
+  \hline \pagebreak 
  \hdltablesection{External TX timestamp interface}\\
  \hline
  timestamps\_o & out & rec & Record-based output ports for

--- a/doc/wbgen/.wrc_diags.tex.swo
+++ b/doc/wbgen/.wrc_diags.tex.swo
--- a/doc/wbgen/wr_streamers_wb.tex
+++ b/doc/wbgen/wr_streamers_wb.tex
--- a/doc/wbgen/wrc_diags.tex
+++ b/doc/wbgen/wrc_diags.tex
--- a/doc/wrpc.tex
+++ b/doc/wrpc.tex
 \documentclass[a4paper, 12pt]{article}
 \usepackage[english]{babel}
 \usepackage{fullpage}
+\usepackage[table,x11names,dvipsnames,table]{xcolor}
 \usepackage{pgf}
 \usepackage{tikz}
 \usepackage[pdftex]{hyperref}  % makes cross references and URLs clickable
@@ -388,6 +389,11 @@ synthesized in section \ref{HDL synthesis}. You can skip this section, unless
 you need to make some custom changes to the LM32 software and compile it
 yourself.\\

+\textbf{Note:} To compile also the host tools that come with this software
+package you will need a \emph{readline-dev} library. In some Linux distributions
+you would have to install it manually. E.g. in Ubuntu, please install
+\emph{libreadline-dev} package.\\
+
 First, you need to download and unpack the LM32 toolchain from the location
 mentioned in section \ref{Repositories and Releases}. The following example
 uses 32bit version of a toolchain. If you encounter problems running it, please
@@ -481,7 +487,7 @@ slot.\\
 \begin{lstlisting}
 $ git clone git://ohwr.org/fmc-projects/spec/spec-sw.git <your_location>/spec-sw
 $ cd <your_location>/spec-sw
-$ git checkout aff79eb
+$ git checkout 0745464
 $ make
 \end{lstlisting}

@@ -1065,7 +1071,7 @@ To verify that database is empty:
 \end{lstlisting}

 % ==========================================================================
-
+\newpage
 \subsection{Syslog}
 \label{Syslog}

@@ -2195,4 +2201,29 @@ in file \texttt{snmp\_test\_config.bash}.
 These tests have to be executed after any changes are made to the \textit{Mini SNMP
 responder}.

+% --------------------------------------------------------------------------
+\newpage
+\section{Wishbone Memory Maps}
+\label{sec:wb_mem_maps}
+
+This appendix provides a register map of Wishbone modules that are exposed to
+external applications/HDL core. In the table below you can see the list of
+modules available on the External Wishbone interface of the WR PTP Core. Please
+bare in mind that WR Streamers Diagnostics module is available only when
+\tts{STREAMERS} external fabric mode is selected.
+\begin{center}
+\begin{tabular}{|l|l|}
+  \hline
+  module name & base address\\
+  \hline \hline
+  WR Core Diagnostics & 0x20800\\
+  WR Streamers Diagnostics & 0x20700\\
+  \hline
+\end{tabular}
+\end{center}
+
+\input{wbgen/wrc_diags.tex}
+\newpage
+\input{wbgen/wr_streamers_wb.tex}
+
 \end{document}