Commit 655586e7 authored by Peter Jansweijer's avatar Peter Jansweijer

SPEC7 has 16 bit PHY, define BOARD_DIVIDE_DMTD_CLOCKS

parent c2d85ad4
Pipeline #318 failed with stages
in 9 seconds
......@@ -53,11 +53,9 @@
#define NUM_AUX_CLOCKS 1
/* spll parameter that are board-specific */
#ifdef CONFIG_TARGET_GENERIC_PHY_16BIT
// SPEC7 has GENERIC_PHY_16BIT
# define BOARD_DIVIDE_DMTD_CLOCKS 0
#else
# define BOARD_DIVIDE_DMTD_CLOCKS 1
#endif
#define BOARD_MAX_CHAN_REF 1
#define BOARD_MAX_CHAN_AUX 2
#define BOARD_MAX_PTRACKERS 1
......
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