Commit 740be374 authored by Benoit Rat's avatar Benoit Rat

wrs: disable 10MHz output (CLK1) until PLL is resync with WR.

parent 20cfb1c0
...@@ -260,6 +260,7 @@ int ad9516_init(int scb_version) ...@@ -260,6 +260,7 @@ int ad9516_init(int scb_version)
* Output 8 => 10 MHz * Output 8 => 10 MHz
* Output 9 => 10 MHz * Output 9 => 10 MHz
*/ */
ad9516_write_reg(0x143, 0x1); //Temporary Powerdown 10MHz output
} else { //Old one } else { //Old one
......
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