Commit 7ca78545 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'greg-sdbfs' into proposed_master

parents 76f60f14 4ef5cb42
......@@ -229,12 +229,21 @@ config SDB_STORAGE
Use SDB to manage flash and eeproms (both W1 and I2C). If not, legacy code
(eeprom only) will be selected.
config GENSDBFS
depends on SDB_STORAGE
default y
boolean "Shell command for SDBFS generation"
help
This option adds _sdb fs_ command to write empty SDBFS filesystem
image in Flash/EEPROM.
config LEGACY_EEPROM
depends on WR_NODE
boolean
default !SDB_STORAGE
config VLAN
depends on WR_NODE
boolean "Filter and rx/tx frames in a VLAN (as opposed to untagged)"
config VLAN_NR
......@@ -280,6 +289,7 @@ config WR_NODE_SIM
these frames.
config ABSCAL
depends on WR_NODE
default y
boolean "Support absolute calibration"
help
......
......@@ -76,6 +76,10 @@ pfilter-y := rules-novlan.bin
pfilter-$(CONFIG_VLAN) += rules-vlan.bin
export pfilter-y
# sdbfs image
sdbfsimg-y := sdbfs-default.bin
export sdbfsimg-y
all:
include shell/shell.mk
......
......@@ -8,6 +8,8 @@ CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
CONFIG_PLL_VERBOSE=y
CONFIG_PFILTER_VERBOSE=y
CONFIG_WRC_VERBOSE=y
......@@ -22,7 +24,6 @@ CONFIG_EMBEDDED_NODE=y
# CONFIG_WR_NODE_PCS16 is not set
CONFIG_STACKSIZE=2048
CONFIG_PPSI=y
CONFIG_UART=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=4455
CONFIG_LATENCY_SYSLOG=y
......@@ -30,6 +31,7 @@ CONFIG_P2P=y
CONFIG_IP=y
CONFIG_CMD_CONFIG=y
CONFIG_SYSLOG=y
# CONFIG_PUTS_SYSLOG is not set
CONFIG_SNMP=y
CONFIG_SNMP_SET=y
CONFIG_BUILD_INIT=y
......@@ -39,17 +41,18 @@ CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
#
# wrpc-sw is tainted if you change the following options
#
CONFIG_DEVELOPER=y
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
CONFIG_CMD_LL=y
# CONFIG_DAC_LOG is not set
CONFIG_CHECK_RESET=y
CONFIG_SPLL_FIFO_LOG=y
CONFIG_PRINTF_IS_XINT=y
......@@ -58,7 +61,6 @@ CONFIG_PRINTF_IS_XINT=y
# CONFIG_PRINTF_IS_NONE is not set
CONFIG_ASSERT=y
CONFIG_DETERMINISTIC_BINARY=y
CONFIG_UART_SW=y
CONFIG_NET_VERBOSE=y
# CONFIG_SNMP_VERBOSE is not set
CONFIG_FAKE_TEMPERATURES=y
......@@ -68,3 +70,4 @@ CONFIG_PRINTF_XINT=y
# CONFIG_PRINTF_FULL is not set
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
# CONFIG_LLDP is not set
......@@ -8,6 +8,8 @@ CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_PLL_VERBOSE is not set
# CONFIG_PFILTER_VERBOSE is not set
# CONFIG_WRC_VERBOSE is not set
......@@ -22,7 +24,6 @@ CONFIG_EMBEDDED_NODE=y
# CONFIG_WR_NODE_PCS16 is not set
CONFIG_STACKSIZE=10240
CONFIG_PPSI=y
CONFIG_UART=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
CONFIG_LATENCY_SYSLOG=y
......@@ -30,6 +31,7 @@ CONFIG_LATENCY_SYSLOG=y
CONFIG_IP=y
CONFIG_CMD_CONFIG=y
CONFIG_SYSLOG=y
# CONFIG_PUTS_SYSLOG is not set
# CONFIG_SNMP is not set
# CONFIG_BUILD_INIT is not set
CONFIG_INIT_COMMAND=""
......@@ -38,17 +40,18 @@ CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
#
# wrpc-sw is tainted if you change the following options
#
CONFIG_DEVELOPER=y
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
CONFIG_CMD_LL=y
# CONFIG_DAC_LOG is not set
CONFIG_CHECK_RESET=y
# CONFIG_SPLL_FIFO_LOG is not set
CONFIG_PRINTF_IS_XINT=y
......@@ -57,7 +60,6 @@ CONFIG_PRINTF_IS_XINT=y
# CONFIG_PRINTF_IS_NONE is not set
# CONFIG_ASSERT is not set
# CONFIG_DETERMINISTIC_BINARY is not set
# CONFIG_UART_SW is not set
# CONFIG_NET_VERBOSE is not set
# CONFIG_FAKE_TEMPERATURES is not set
CONFIG_LATENCY_PROBE=y
......@@ -66,3 +68,4 @@ CONFIG_PRINTF_XINT=y
# CONFIG_PRINTF_FULL is not set
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
# CONFIG_LLDP is not set
......@@ -8,6 +8,8 @@ CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_PLL_VERBOSE is not set
# CONFIG_PFILTER_VERBOSE is not set
# CONFIG_WRC_VERBOSE is not set
......@@ -22,7 +24,6 @@ CONFIG_EMBEDDED_NODE=y
# CONFIG_WR_NODE_PCS16 is not set
CONFIG_STACKSIZE=10240
CONFIG_PPSI=y
CONFIG_UART=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
CONFIG_LATENCY_SYSLOG=y
......@@ -30,6 +31,7 @@ CONFIG_P2P=y
CONFIG_IP=y
CONFIG_CMD_CONFIG=y
CONFIG_SYSLOG=y
# CONFIG_PUTS_SYSLOG is not set
# CONFIG_SNMP is not set
# CONFIG_BUILD_INIT is not set
CONFIG_INIT_COMMAND=""
......@@ -38,17 +40,18 @@ CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
#
# wrpc-sw is tainted if you change the following options
#
CONFIG_DEVELOPER=y
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
CONFIG_CMD_LL=y
# CONFIG_DAC_LOG is not set
CONFIG_CHECK_RESET=y
# CONFIG_SPLL_FIFO_LOG is not set
CONFIG_PRINTF_IS_XINT=y
......@@ -57,7 +60,6 @@ CONFIG_PRINTF_IS_XINT=y
# CONFIG_PRINTF_IS_NONE is not set
# CONFIG_ASSERT is not set
# CONFIG_DETERMINISTIC_BINARY is not set
# CONFIG_UART_SW is not set
# CONFIG_NET_VERBOSE is not set
# CONFIG_FAKE_TEMPERATURES is not set
CONFIG_LATENCY_PROBE=y
......@@ -66,3 +68,4 @@ CONFIG_PRINTF_XINT=y
# CONFIG_PRINTF_FULL is not set
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
# CONFIG_LLDP is not set
......@@ -37,9 +37,11 @@ CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
CONFIG_AUX_DIAG=y
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
CONFIG_WR_DIAG=y
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
#
# wrpc-sw is tainted if you change the following options
......
......@@ -8,33 +8,40 @@ CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
CONFIG_VLAN_FOR_CLASS6=0
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
CONFIG_VLAN=y
CONFIG_VLAN_NR=1
CONFIG_VLAN_1_FOR_CLASS7=10
CONFIG_VLAN_2_FOR_CLASS7=11
CONFIG_VLAN_FOR_CLASS6=20
# CONFIG_HOST_PROCESS is not set
CONFIG_LM32=y
CONFIG_EMBEDDED_NODE=y
# CONFIG_WR_NODE_PCS16 is not set
CONFIG_STACKSIZE=2048
CONFIG_PPSI=y
CONFIG_UART=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
CONFIG_P2P=y
# CONFIG_IP is not set
CONFIG_IP=y
# CONFIG_CMD_CONFIG is not set
# CONFIG_BUILD_INIT is not set
CONFIG_INIT_COMMAND=""
CONFIG_HAS_BUILD_INIT=0
# CONFIG_SYSLOG is not set
CONFIG_SNMP=y
CONFIG_SNMP_SET=y
CONFIG_SNMP_AUX_DIAG=y
CONFIG_BUILD_INIT=y
CONFIG_INIT_COMMAND="vlan off;ptp stop;sfp match;mode slave;ptp start"
CONFIG_HAS_BUILD_INIT=1
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
CONFIG_AUX_DIAG=y
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
# CONFIG_WR_DIAG is not set
CONFIG_WR_DIAG=y
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
#
# wrpc-sw is tainted if you change the following options
......
......@@ -8,9 +8,10 @@ CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=65536
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
CONFIG_PLL_VERBOSE=y
CONFIG_WRC_VERBOSE=y
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
......@@ -18,18 +19,17 @@ CONFIG_VLAN_FOR_CLASS6=0
# CONFIG_HOST_PROCESS is not set
CONFIG_LM32=y
# CONFIG_EMBEDDED_NODE is not set
CONFIG_UART=y
CONFIG_LATENCY_ETHTYPE=291
CONFIG_INIT_COMMAND=""
CONFIG_HAS_BUILD_INIT=0
CONFIG_HAS_FLASH_INIT=0
# CONFIG_FLASH_INIT is not set
# CONFIG_AUX_DIAG is not set
#
# wrpc-sw is tainted if you change the following options
#
# CONFIG_DEVELOPER is not set
# CONFIG_CHECK_RESET is not set
# CONFIG_DETERMINISTIC_BINARY is not set
CONFIG_VLAN_ARRAY_SIZE=1
CONFIG_PRINTF_XINT=y
# CONFIG_PRINTF_FULL is not set
......
......@@ -8,35 +8,39 @@ CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
# CONFIG_VLAN is not set
CONFIG_VLAN_NR=0
CONFIG_VLAN_1_FOR_CLASS7=0
CONFIG_VLAN_2_FOR_CLASS7=0
CONFIG_VLAN_FOR_CLASS6=0
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
CONFIG_VLAN=y
CONFIG_VLAN_NR=1
CONFIG_VLAN_1_FOR_CLASS7=10
CONFIG_VLAN_2_FOR_CLASS7=11
CONFIG_VLAN_FOR_CLASS6=20
# CONFIG_HOST_PROCESS is not set
CONFIG_LM32=y
CONFIG_EMBEDDED_NODE=y
# CONFIG_WR_NODE_PCS16 is not set
CONFIG_STACKSIZE=2048
CONFIG_PPSI=y
CONFIG_UART=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
# CONFIG_P2P is not set
CONFIG_IP=y
# CONFIG_CMD_CONFIG is not set
# CONFIG_SYSLOG is not set
# CONFIG_SNMP is not set
# CONFIG_BUILD_INIT is not set
CONFIG_INIT_COMMAND=""
CONFIG_HAS_BUILD_INIT=0
CONFIG_SNMP=y
CONFIG_SNMP_SET=y
CONFIG_BUILD_INIT=y
CONFIG_INIT_COMMAND="vlan off;ptp stop;sfp match;mode slave;ptp start"
CONFIG_HAS_BUILD_INIT=1
CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
# CONFIG_WR_DIAG is not set
# CONFIG_WR_NODE_SIM is not set
CONFIG_ABSCAL=y
#
# wrpc-sw is tainted if you change the following options
......
......@@ -8,6 +8,8 @@ CONFIG_PPSI_FORCE_CONFIG=y
CONFIG_PRINT_BUFSIZE=128
CONFIG_RAMSIZE=131072
CONFIG_TEMP_POLL_INTERVAL=15
CONFIG_TEMP_HIGH_THRESHOLD=70
CONFIG_TEMP_HIGH_RAPPEL=60
# CONFIG_PLL_VERBOSE is not set
# CONFIG_PFILTER_VERBOSE is not set
# CONFIG_WRC_VERBOSE is not set
......@@ -22,7 +24,6 @@ CONFIG_EMBEDDED_NODE=y
# CONFIG_WR_NODE_PCS16 is not set
CONFIG_STACKSIZE=2048
CONFIG_PPSI=y
CONFIG_UART=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
# CONFIG_P2P is not set
......@@ -35,15 +36,18 @@ CONFIG_HAS_FLASH_INIT=1
CONFIG_FLASH_INIT=y
# CONFIG_AUX_DIAG is not set
CONFIG_SDB_STORAGE=y
CONFIG_GENSDBFS=y
# CONFIG_LEGACY_EEPROM is not set
# CONFIG_WR_DIAG is not set
CONFIG_WR_NODE_SIM=y
CONFIG_ABSCAL=y
#
# wrpc-sw is tainted if you change the following options
#
CONFIG_DEVELOPER=y
# CONFIG_CMD_LL is not set
# CONFIG_DAC_LOG is not set
# CONFIG_CHECK_RESET is not set
# CONFIG_SPLL_FIFO_LOG is not set
CONFIG_PRINTF_IS_XINT=y
......@@ -52,7 +56,6 @@ CONFIG_PRINTF_IS_XINT=y
# CONFIG_PRINTF_IS_NONE is not set
# CONFIG_ASSERT is not set
# CONFIG_DETERMINISTIC_BINARY is not set
# CONFIG_UART_SW is not set
# CONFIG_NET_VERBOSE is not set
# CONFIG_FAKE_TEMPERATURES is not set
# CONFIG_LATENCY_PROBE is not set
......@@ -61,3 +64,4 @@ CONFIG_PRINTF_XINT=y
# CONFIG_PRINTF_FULL is not set
# CONFIG_PRINTF_MINI is not set
# CONFIG_PRINTF_NONE is not set
# CONFIG_LLDP is not set
......@@ -39,5 +39,11 @@ obj-y += $(pfilter-y:.bin=.o)
rules-%.o: rules-%.bin
$(OBJCOPY) -I binary $(OBJCOPY-TARGET-y) $< $@
# sdbfs image
obj-y += $(sdbfsimg-y:.bin=.o)
sdbfs-default.o: tools/sdbfs-default.bin
$(OBJCOPY) -I binary $(OBJCOPY-TARGET-y) $< $@
$(pfilter-y): tools
tools/pfilter-builder
......@@ -9,6 +9,7 @@
#include <wrc.h>
#include <flash.h>
#include <types.h>
#include <storage.h>
#define SDBFS_BIG_ENDIAN
#include <libsdbfs.h>
......@@ -19,6 +20,7 @@
static void delay(void)
{
int i;
for (i = 0; i < (int)(CPU_CLOCK/10000000); i++)
asm volatile ("nop");
}
......@@ -54,7 +56,7 @@ static uint8_t bbspi_transfer(int cspin, uint8_t val)
/*
* Init function (just set the SPI pins for idle)
*/
void flash_init()
void flash_init(void)
{
gpio_out(GPIO_SPI_NCS, 1);
gpio_out(GPIO_SPI_SCLK, 0);
......@@ -68,17 +70,17 @@ int flash_write(uint32_t addr, uint8_t *buf, int count)
{
int i;
bbspi_transfer(1,0);
bbspi_transfer(0,0x06);
bbspi_transfer(1,0);
bbspi_transfer(0,0x02);
bbspi_transfer(0,(addr & 0xFF0000) >> 16);
bbspi_transfer(0,(addr & 0xFF00) >> 8);
bbspi_transfer(0,(addr & 0xFF));
for ( i = 0; i < count; i++ ) {
bbspi_transfer(0,buf[i]);
bbspi_transfer(1, 0);
bbspi_transfer(0, 0x06);
bbspi_transfer(1, 0);
bbspi_transfer(0, 0x02);
bbspi_transfer(0, (addr & 0xFF0000) >> 16);
bbspi_transfer(0, (addr & 0xFF00) >> 8);
bbspi_transfer(0, (addr & 0xFF));
for (i = 0; i < count; i++) {
bbspi_transfer(0, buf[i]);
}
bbspi_transfer(1,0);
bbspi_transfer(1, 0);
/* make sure the write is complete */
while (flash_rsr() & 0x01) {
......@@ -94,16 +96,17 @@ int flash_write(uint32_t addr, uint8_t *buf, int count)
int flash_read(uint32_t addr, uint8_t *buf, int count)
{
int i;
bbspi_transfer(1,0);
bbspi_transfer(0,0x0b);
bbspi_transfer(0,(addr & 0xFF0000) >> 16);
bbspi_transfer(0,(addr & 0xFF00) >> 8);
bbspi_transfer(0,(addr & 0xFF));
bbspi_transfer(0,0);
for ( i = 0; i < count; i++ ) {
bbspi_transfer(1, 0);
bbspi_transfer(0, 0x0b);
bbspi_transfer(0, (addr & 0xFF0000) >> 16);
bbspi_transfer(0, (addr & 0xFF00) >> 8);
bbspi_transfer(0, (addr & 0xFF));
bbspi_transfer(0, 0);
for (i = 0; i < count; i++) {
buf[i] = bbspi_transfer(0, 0);
}
bbspi_transfer(1,0);
bbspi_transfer(1, 0);
return count;
}
......@@ -114,15 +117,16 @@ int flash_erase(uint32_t addr, int count)
int sectors;
/*calc number of sectors to be removed*/
if(count % FLASH_BLOCKSIZE > 0)
if (count % storage_cfg.blocksize > 0)
sectors = 1;
else
sectors = 0;
sectors += (count / FLASH_BLOCKSIZE);
sectors += (count / storage_cfg.blocksize);
for(i=0; i<sectors; ++i) {
flash_serase(addr + i*FLASH_BLOCKSIZE);
while(flash_rsr() & 0x01);
for (i = 0; i < sectors; ++i) {
flash_serase(addr + i*storage_cfg.blocksize);
while (flash_rsr() & 0x01)
;
}
return count;
......@@ -133,45 +137,46 @@ int flash_erase(uint32_t addr, int count)
*/
void flash_serase(uint32_t addr)
{
bbspi_transfer(1,0);
bbspi_transfer(0,0x06);
bbspi_transfer(1,0);
bbspi_transfer(0,0xD8);
bbspi_transfer(0,(addr & 0xFF0000) >> 16);
bbspi_transfer(0,(addr & 0xFF00) >> 8);
bbspi_transfer(0,(addr & 0xFF));
bbspi_transfer(1,0);
bbspi_transfer(1, 0);
bbspi_transfer(0, 0x06);
bbspi_transfer(1, 0);
bbspi_transfer(0, 0xD8);
bbspi_transfer(0, (addr & 0xFF0000) >> 16);
bbspi_transfer(0, (addr & 0xFF00) >> 8);
bbspi_transfer(0, (addr & 0xFF));
bbspi_transfer(1, 0);
}
/*
* Bulk erase
*/
void
flash_berase()
flash_berase(void)
{
bbspi_transfer(1,0);
bbspi_transfer(0,0x06);
bbspi_transfer(1,0);
bbspi_transfer(0,0xc7);
bbspi_transfer(1,0);
bbspi_transfer(1, 0);
bbspi_transfer(0, 0x06);
bbspi_transfer(1, 0);
bbspi_transfer(0, 0xc7);
bbspi_transfer(1, 0);
}
/*
* Read status register
*/
uint8_t flash_rsr()
uint8_t flash_rsr(void)
{
uint8_t retval;
bbspi_transfer(1,0);
bbspi_transfer(0,0x05);
retval = bbspi_transfer(0,0);
bbspi_transfer(1,0);
bbspi_transfer(1, 0);
bbspi_transfer(0, 0x05);
retval = bbspi_transfer(0, 0);
bbspi_transfer(1, 0);
return retval;
}
/*****************************************************************************/
/* SDB */
/* SDB */
/*****************************************************************************/
/* The sdb filesystem itself */
......@@ -202,7 +207,8 @@ static void flash_sdb_list(struct sdbfs *fs)
{
struct sdb_device *d;
int new = 1;
while ( (d = sdbfs_scan(fs, new)) != NULL) {
while ((d = sdbfs_scan(fs, new)) != NULL) {
d->sdb_component.product.record_type = '\0';
pp_printf("file 0x%08x @ %4i, name %19s\n",
(int)(d->sdb_component.product.device_id),
......@@ -215,19 +221,19 @@ static void flash_sdb_list(struct sdbfs *fs)
/*
* Check for SDB presence on flash
*/
int flash_sdb_check()
int flash_sdb_check(void)
{
uint32_t magic = 0;
int i;
uint32_t entry_point[] = {
0x000000, // flash base
0x100, // second page in flash
0x200, // IPMI with MultiRecord
0x300, // IPMI with larger MultiRecord
0x170000, // after first FPGA bitstream
0x2e0000 // after MultiBoot bitstream
};
0x000000, /* flash base */
0x100, /* second page in flash */
0x200, /* IPMI with MultiRecord */
0x300, /* IPMI with larger MultiRecord */
0x170000, /* after first FPGA bitstream */
0x2e0000 /* after MultiBoot bitstream */
};
for (i = 0; i < ARRAY_SIZE(entry_point); i++) {
flash_read(entry_point[i], (uint8_t *)&magic, 4);
......
......@@ -7,6 +7,7 @@
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <errno.h>
#include <wrc.h>
#include <w1.h>
#include <storage.h>
......@@ -15,6 +16,7 @@
#include "i2c.h"
#include "onewire.h"
#include "endpoint.h"
#include "syscon.h"
#include <sdb.h>
#define SDBFS_BIG_ENDIAN
......@@ -35,6 +37,8 @@
#define EEPROM_START_ADR 0
#define EEPROM_STOP_ADR 127
struct storage_config storage_cfg;
/* Functions for Flash access */
static int sdb_flash_read(struct sdbfs *fs, int offset, void *buf, int count)
{
......@@ -169,6 +173,7 @@ static void storage_sdb_list(struct sdbfs *fs)
{
struct sdb_device *d;
int new = 1;
while ((d = sdbfs_scan(fs, new)) != NULL) {
d->sdb_component.product.record_type = '\0';
pp_printf("file 0x%08x @ %4i, name %s\n",
......@@ -220,7 +225,7 @@ void storage_init(int chosen_i2cif, int chosen_i2c_addr)
pp_printf("sdbfs: found at %i in Flash\n",
entry_points_flash[i]);
wrc_sdb.drvdata = NULL;
wrc_sdb.blocksize = FLASH_BLOCKSIZE;
wrc_sdb.blocksize = storage_cfg.blocksize;
wrc_sdb.entrypoint = entry_points_flash[i];
wrc_sdb.read = sdb_flash_read;
wrc_sdb.write = sdb_flash_write;
......@@ -259,7 +264,7 @@ void storage_init(int chosen_i2cif, int chosen_i2c_addr)
i2c_params.addr = EEPROM_START_ADR;
while (i2c_params.addr <= EEPROM_STOP_ADR) {
/* First, we check if I2C EEPROM is there */
if (!mi2c_devprobe(i2c_params.ifnum, i2c_params.addr)) {
if (!mi2c_devprobe(i2c_params.ifnum, i2c_params.addr)) {
i2c_params.addr++;
continue;
}
......@@ -738,3 +743,164 @@ out:
sdbfs_close(&wrc_sdb);
return ret;
}
int storage_read_hdl_cfg(void)
{
get_storage_info(&storage_cfg.memtype, &storage_cfg.baseadr,
&storage_cfg.blocksize);
if (storage_cfg.memtype == MEM_FLASH && storage_cfg.blocksize == 0) {
storage_cfg.valid = 0;
/* keep default blocksize for backwards compatibility */
storage_cfg.blocksize = FLASH_BLOCKSIZE;
} else
storage_cfg.valid = 1;
return 0;
}
#ifdef CONFIG_GENSDBFS
extern uint32_t _binary_tools_sdbfs_default_bin_start[];
extern uint32_t _binary_tools_sdbfs_default_bin_end[];
static inline unsigned long SDB_ALIGN(unsigned long x, int blocksize)
{
return (x + (blocksize - 1)) & ~(blocksize - 1);
}
int storage_sdbfs_erase(int mem_type, uint32_t base_adr, uint32_t blocksize,
uint8_t i2c_adr)
{
if (mem_type == MEM_FLASH && blocksize == 0)
return -EINVAL;
if (mem_type == MEM_FLASH) {
pp_printf("Erasing Flash(0x%x)...\n", base_adr);
sdb_flash_erase(NULL, base_adr, SDBFS_REC * blocksize);
} else if (mem_type == MEM_EEPROM) {
pp_printf("Erasing EEPROM %d (0x%x)...\n", i2c_adr, base_adr);
i2c_params.ifnum = WRPC_FMC_I2C;
i2c_params.addr = i2c_adr;
wrc_sdb.drvdata = &i2c_params;
sdb_i2c_erase(&wrc_sdb, base_adr, SDBFS_REC *
sizeof(struct sdb_device));
} else if (mem_type == MEM_1W_EEPROM) {
pp_printf("Erasing 1-W EEPROM (0x%x)...\n", base_adr);
wrc_sdb.drvdata = &wrpc_w1_bus;
sdb_w1_erase(&wrc_sdb, base_adr, SDBFS_REC *
sizeof(struct sdb_device));
}
return 0;
}
int storage_gensdbfs(int mem_type, uint32_t base_adr, uint32_t blocksize,
uint8_t i2c_adr)
{
struct sdb_device *sdbfs =
(struct sdb_device *) _binary_tools_sdbfs_default_bin_start;
struct sdb_interconnect *sdbfs_dir = (struct sdb_interconnect *)
_binary_tools_sdbfs_default_bin_start;
/* struct sdb_device sdbfs_buf[SDBFS_REC]; */
int i;
char buf[19] = {0};
int cur_adr, size;
uint32_t val;
if (mem_type == MEM_FLASH && base_adr == 0)
return -EINVAL;
if (mem_type == MEM_FLASH && blocksize == 0)
return -EINVAL;
/* first file starts after the SDBFS description */
cur_adr = base_adr + SDB_ALIGN(SDBFS_REC*sizeof(struct sdb_device),
blocksize);
/* scan through files */
for (i = 1; i < SDBFS_REC; ++i) {
/* relocate each file depending on base address and block size*/
size = sdbfs[i].sdb_component.addr_last -
sdbfs[i].sdb_component.addr_first;
sdbfs[i].sdb_component.addr_first = cur_adr;
sdbfs[i].sdb_component.addr_last = cur_adr + size;
cur_adr = SDB_ALIGN(cur_adr + (size + 1), blocksize);
}
/* update the directory */
sdbfs_dir->sdb_component.addr_first = base_adr;
sdbfs_dir->sdb_component.addr_last =
sdbfs[SDBFS_REC-1].sdb_component.addr_last;
for (i = 0; i < SDBFS_REC; ++i) {
strncpy(buf, (char *)sdbfs[i].sdb_component.product.name, 18);
pp_printf("filename: %s; first: %x; last: %x\n", buf,
(int)sdbfs[i].sdb_component.addr_first,
(int)sdbfs[i].sdb_component.addr_last);
}
size = sizeof(struct sdb_device);
if (mem_type == MEM_FLASH) {
pp_printf("Formatting SDBFS in Flash(0x%x)...\n", base_adr);
/* each file is in a separate block, therefore erase SDBFS_REC
* number of blocks */
sdb_flash_erase(NULL, base_adr, SDBFS_REC * blocksize);
for (i = 0; i < SDBFS_REC; ++i) {
sdb_flash_write(NULL, base_adr + i*size, &sdbfs[i],
size);
}
/*
pp_printf("Verification...");
sdb_flash_read(NULL, base_adr, sdbfs_buf, SDBFS_REC *
sizeof(struct sdb_device));
if(memcmp(sdbfs, sdbfs_buf, SDBFS_REC *
sizeof(struct sdb_device)))
pp_printf("Error.\n");
else
pp_printf("OK.\n");
*/
} else if (mem_type == MEM_EEPROM) {
/* First, check if EEPROM is really there */
if (!mi2c_devprobe(WRPC_FMC_I2C, i2c_adr)) {
pp_printf("I2C EEPROM not found\n");
return -EINVAL;
}
i2c_params.ifnum = WRPC_FMC_I2C;
i2c_params.addr = i2c_adr;
pp_printf("Formatting SDBFS in I2C EEPROM %d (0x%x)...\n",
i2c_params.addr, base_adr);
wrc_sdb.drvdata = &i2c_params;
sdb_i2c_erase(&wrc_sdb, base_adr, SDBFS_REC * size);
for (i = 0; i < SDBFS_REC; ++i) {
sdb_i2c_write(&wrc_sdb, base_adr + i*size, &sdbfs[i],
size);
}
/*
pp_printf("Verification...");
sdb_i2c_read(&wrc_sdb, base_adr, sdbfs_buf, SDBFS_REC *
sizeof(struct sdb_device));
if(memcmp(sdbfs, sdbfs_buf, SDBFS_REC *
sizeof(struct sdb_device)))
pp_printf("Error.\n");
else
pp_printf("OK.\n");
*/
} else if (mem_type == MEM_1W_EEPROM) {
wrc_sdb.drvdata = &wrpc_w1_bus;
if (sdb_w1_read(&wrc_sdb, 0, &val, sizeof(val)) !=
sizeof(val)) {
pp_printf("1-Wire EEPROM not found\n");
return -EINVAL;
}
pp_printf("Formatting SDBFS in 1-W EEPROM (0x%x)...\n",
base_adr);
sdb_w1_erase(&wrc_sdb, base_adr, SDBFS_REC * size);
for (i = 0; i < SDBFS_REC; ++i) {
sdb_w1_write(&wrc_sdb, base_adr + i*size, &sdbfs[i],
size);
}
}
/* re-initialize storage after writing sdbfs image */
storage_init(WRPC_FMC_I2C, FMC_EEPROM_ADR);
return mem_type;
}
#endif
......@@ -28,6 +28,17 @@ void get_hw_name(char *str)
memcpy(str, &val, HW_NAME_LENGTH-1);
}
/****************************
* Flash info
***************************/
void get_storage_info(int *memtype, uint32_t *sdbfs_baddr, uint32_t *blocksize)
{
/* convert sector size from KB to bytes */
*blocksize = SYSC_HWFR_STORAGE_SEC_R(syscon->HWFR) * 1024;
*sdbfs_baddr = syscon->SDBFS;
*memtype = SYSC_HWFR_STORAGE_TYPE_R(syscon->HWFR);
}
/****************************
* TIMER
***************************/
......@@ -50,7 +61,9 @@ void timer_delay(uint32_t tics)
{
uint32_t t_end;
// timer_init(1);
/*
timer_init(1);
*/
t_end = timer_get_tics() + tics;
while (time_before(timer_get_tics(), t_end))
......@@ -124,16 +137,16 @@ void net_rst(void)
int wdiag_set_valid(int enable)
{
if(enable)
if (enable)
syscon->WDIAG_CTRL |= SYSC_WDIAG_CTRL_DATA_VALID;
if(!enable)
if (!enable)
syscon->WDIAG_CTRL &= ~SYSC_WDIAG_CTRL_DATA_VALID;
return (int)(syscon->WDIAG_CTRL & SYSC_WDIAG_CTRL_DATA_VALID);
}
int wdiag_get_valid(void)
{
if(syscon->WDIAG_CTRL & SYSC_WDIAG_CTRL_DATA_VALID)
if (syscon->WDIAG_CTRL & SYSC_WDIAG_CTRL_DATA_VALID)
return 1;
else
return 0;
......@@ -141,15 +154,15 @@ int wdiag_get_valid(void)
int wdiag_get_snapshot(void)
{
if(syscon->WDIAG_CTRL & SYSC_WDIAG_CTRL_DATA_SNAPSHOT)
if (syscon->WDIAG_CTRL & SYSC_WDIAG_CTRL_DATA_SNAPSHOT)
return 1;
else
return 0;
}
void wdiags_write_servo_state(int wr_mode, uint8_t servostate, uint64_t mu,
uint64_t dms, int32_t asym, int32_t cko, int32_t setp,
int32_t ucnt)
uint64_t dms, int32_t asym, int32_t cko,
int32_t setp, int32_t ucnt)
{
syscon->WDIAG_SSTAT = wr_mode ? SYSC_WDIAG_SSTAT_WR_MODE:0;
syscon->WDIAG_SSTAT |= SYSC_WDIAG_SSTAT_SERVOSTATE_W(servostate);
......@@ -166,6 +179,7 @@ void wdiags_write_servo_state(int wr_mode, uint8_t servostate, uint64_t mu,
void wdiags_write_port_state(int link, int locked)
{
uint32_t val = 0;
val = link ? SYSC_WDIAG_PSTAT_LINK : 0;
val |= locked ? SYSC_WDIAG_PSTAT_LOCKED : 0;
syscon->WDIAG_PSTAT = val;
......@@ -196,5 +210,5 @@ void wdiags_write_time(uint64_t sec, uint32_t nsec)
void wdiags_write_temp(uint32_t temp)
{
syscon->WDIAG_TEMP=temp;
syscon->WDIAG_TEMP = temp;
}
......@@ -66,6 +66,12 @@ their own BSP, can find the board-common module under:
\cline{1-3}
g\_with\_external\_clock\_input & boolean & true & \\
\cline{1-3}
g\_board\_name & string & "NA " & \\
\cline{1-3}
g\_flash\_secsz\_kb & integer & 256 & \\
\cline{1-3}
g\_flash\_sdbfs\_baddr & integer & 0x600000 & \\
\cline{1-3}
g\_aux\_clks & integer & 0 & \\
\cline{1-3}
g\_dpram\_initf & string & "" & \\
......
......@@ -8,6 +8,17 @@
g\_with\_external\_clock\_input & boolean & false &
enable external clock and 1-PPS inputs. The PLL inside WRPC will lock to
external 10 MHz and 1-PPS signal when operating in GrandMaster mode\\
\hline
g\_board\_name & string & "NA " & board name, exported by WRPC software as
SNMP object for diagnostics\\
\hline
g\_flash\_secsz\_kb & integer & 256 & Flash memory sector size in kilobytes.
Available through a Wishbone register, used by WRPC software to read/write
SDBFS image\\
\hline
g\_flash\_sdbfs\_baddr & integer & 0x600000 & Default base address in Flash
memory where \code{sdb fs} command should store an empty SDBFS image\\
\hline
g\_phys\_uart & boolean & true & enable physical UART interface\\
\hline
g\_virtual\_uart & boolean & false & enable virtual UART interface\\
......
......@@ -29,7 +29,7 @@
\hline
rst\_n\_i & in & 1 & main reset input, active-low (hold for at least 5
\tts{clk\_sys\_i} cycles)\\
\hline
\hline\pagebreak
\hdltablesection{Timing system}\\
\hline
dac\_hpll\_load\_p1\_o & out & 1 & validates DAC value on data port \\
......@@ -89,7 +89,7 @@
when \tts{g\_pcs\_16bit = true}}\\
\cline{1-3}
phy16\_i & in & rec & \\
\hline
\hline\pagebreak
\hdltablesection{GPIO}\\
\hline
led\_act\_o & out & 1 & signal for driving Ethernet activity LED\\
......@@ -103,7 +103,7 @@
scl\_i & in & 1 & \\
\cline{1-3}
scl\_o & out & 1 & \\
\hline\pagebreak
\hline
sfp\_sda\_i & in & 1 & \multirowpar{4}{I2C interface for EEPROM inside SFP module}\\
\cline{1-3}
sfp\_sda\_o & out & 1 & \\
......
......@@ -555,35 +555,6 @@ Among plenty of messages you should be able to find something very similar to:
[1275527.296757] Product name: FmcDio5cha
\end{lstlisting}
By default, when loading the \textit{spec.ko} driver, FPGA gets programmed with
the "golden" bitstream. Starting from version 3.0, WR PTP Core uses a flash
memory chip on the carrier as a default place for storing the calibration
parameters and the init script. Also the storage format of this information is
now better organized in the files of the SDBFS filesystem. Therefore, starting
from v3.0 you have to write the SDBFS filesystem image to the flash
before running the WRPC. You can download the image from \textit{ohwr.org}:
\begin{lstlisting}
$ wget http://www.ohwr.org/attachments/download/4060/sdbfs-flash.bin
\end{lstlisting}
It contains all the files required by the core. They are empty, but have to
exist in the SDBFS structure to be written later as described in section
\ref{Writing configuration}. To write the filesystem image to flash, please
execute the following command:
\begin{lstlisting}
$ sudo tools/flash-write -c 0x0 0 1507712 < <your_location>/sdbfs-flash.bin
\end{lstlisting}
\noindent\textbf{Note:} If you have more than one SPEC board in your computer,
you can use \code{-b} parameter which takes the PCI bus address of the card you
want to program. This can be found in the list of the PCI devices installed in
the system (\code{lspci}).
\noindent\textbf{Note:} Please refer to section \ref{Writing SDBFS image in
standalone configuration} for instructions on how to write the SDBFS image to a
standalone SPEC or custom hardware.\\
Now, you are ready to program the FPGA with your synthesized bitstream from
\texttt{<your\_location>/wr-cores/syn/spec\_ref\_design/spec\_wr\_ref\_top.bin}
\begin{lstlisting}
......@@ -605,9 +576,31 @@ WRPC shell:
\begin{lstlisting}
$ sudo tools/spec-vuart
\end{lstlisting}
If you are able to see the shell prompt \textit{wrc\#} this means the Core
is up and running on your SPEC card. Congratulations !
is up and running on your SPEC card. Congratulations !\\
Starting from version 3.0, WR PTP Core uses a flash memory chip on the carrier
as a default place for storing calibration parameters and an init script.
The storage format of this information is organized in SDBFS filesystem.
Therefore, starting from v3.0 you have to write the empty
SDBFS filesystem image to the flash before running the WRPC. The simplest way of
doing this is by calling a WR PTP Core shell command:
\begin{lstlisting}
wrc# sdb fs 0
\end{lstlisting}
You should see the output similar to:
\begin{lstlisting}[basicstyle=\scriptsize\ttfamily]
filename: . ; first: 2e0000; last: 32007f
filename: wr-init ; first: 2f0000; last: 2f00ff
filename: calibration ; first: 300000; last: 30007f
filename: mac-address ; first: 310000; last: 310005
filename: sfp-database ; first: 320000; last: 32007f
Formatting SDBFS in Flash(0x2e0000)...
\end{lstlisting}
The other two methods: through the PCIe bus and using a Xilinx JTAG cable are
described in appendix \ref{appendix:writing_sdbfs}.
% ==========================================================================
\subsection{Programming FPGA on other boards}
......@@ -1849,6 +1842,34 @@ tools used to build and run it, you can write to our mailing list
\code{sdb} & prints devices connected to the Wishbone bus inside WRPC \\
\code{sdb fs <memtype> <baseadr> <param>} & creates SDBFS image under
specified \code{<baseadr>} in selected storage depending on \code{<memtype>}
({\bf 0} - Flash, {\bf 1} - I2C EEPROM, {\bf 2} - 1-Wire EEPROM). The meaning
of last parameter \code{<param>} depends on the type of selected storage. It
is either the sector size in kilobytes (for Flash) or I2C chip address (for
I2C EEPROM). Command \code{sdb} is available if \texttt{CONFIG\_GENSDBFS}
is set.\\
\code{sdb fs 0} & creates SDBFS image in Flash memory. Base address and sector
size are taken from HDL Syscon registers for SPEC/SVEC boards. If you want
to use it for custom board, base address and sector size must be specified
as VHDL generic parameters of the WR PTP Core. Command \code{sdb} is
available if \texttt{CONFIG\_GENSDBFS} is set.\\
\code{sdb fse <memtype> <baseadr> <param>} & erases SDBFS image under
specified \code{<baseadr>} from selected storage depending on
\code{<memtype>} ({\bf 0} - Flash, {\bf 1} - I2C EEPROM, {\bf 2} - 1-Wire
EEPROM). The meaning of last parameter \code{<param>} depends on the type
of selected storage. It is either the sector size in kilobytes (for Flash)
or I2C chip address (for I2C EEPROM). Command \code{sdb} is available
if \texttt{CONFIG\_GENSDBFS} is set.\\
\code{sdb fse 0} & erases SDBFS image from Flash memory. Base address and sector
size are taken from HDL Syscon registers for SPEC/SVEC boards. If you want
to use it for custom board, base address and sector size must be specified
as VHDL generic parameters of the WR PTP Core. Command \code{sdb} is
available if \texttt{CONFIG\_GENSDBFS} is set.\\
\code{sfp add <PN> <deltaTx> <deltaRx> <alpha>} & stores calibration
parameters for SFP to a file in Flash/EEPROM \\
......@@ -1982,8 +2003,41 @@ tools used to build and run it, you can write to our mailing list
% ##########################################################################
\clearpage
\section{Writing SDBFS image in standalone configuration}
\label{Writing SDBFS image in standalone configuration}
\section{Other ways to write SDBFS image to your Flash memory}
\label{appendix:writing_sdbfs}
\subsection{Writing SDBFS image through PCIe bus}
To write SDBFS filesystem image to the Flash memory of a hosted SPEC card, you
can use the \texttt{flash-write} tool available in the \emph{spec-sw} drivers
package.
First, please download the SDBFS image from \textit{ohwr.org}:
\begin{lstlisting}
$ wget http://www.ohwr.org/attachments/download/4060/sdbfs-flash.bin
\end{lstlisting}
It contains all the files required by the core. They are empty, but have to
exist in the SDBFS structure to be filled later from the WR PTP Core shell or
SNMP.\\
Before calling the tool, you need to have SPEC drivers loaded in your system:
\begin{lstlisting}
$ cd <your_location>/spec-sw
$ sudo insmod fmc-bus/kernel/fmc.ko
$ sudo insmod kernel/spec.ko
\end{lstlisting}
To write the filesystem image to flash, please execute the following
command:
\begin{lstlisting}
$ sudo tools/flash-write -c 0x0 0 1507712 < <your_location>/sdbfs-flash.bin
\end{lstlisting}
\noindent\textbf{Note:} If you have more than one SPEC board in your computer,
you can use \code{-b} parameter which takes the PCI bus address of the card you
want to program. This can be found in the list of the PCI devices installed in
the system (\code{lspci}).
\subsection{Writing SDBFS image in standalone configuration}
If you use SPEC board in a host-less environment, or you use custom
hardware and SPEC drivers/tools cannot be used, there is still a
......
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Mon Jul 3 13:40:08 2017
* Created : Mon Nov 27 13:37:56 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -127,6 +127,18 @@
#define SYSC_HWFR_MEMSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define SYSC_HWFR_MEMSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Storage type in reg: Hardware Feature Register */
#define SYSC_HWFR_STORAGE_TYPE_MASK WBGEN2_GEN_MASK(8, 2)
#define SYSC_HWFR_STORAGE_TYPE_SHIFT 8
#define SYSC_HWFR_STORAGE_TYPE_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define SYSC_HWFR_STORAGE_TYPE_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Storage sector size in reg: Hardware Feature Register */
#define SYSC_HWFR_STORAGE_SEC_MASK WBGEN2_GEN_MASK(16, 16)
#define SYSC_HWFR_STORAGE_SEC_SHIFT 16
#define SYSC_HWFR_STORAGE_SEC_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define SYSC_HWFR_STORAGE_SEC_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Hardware Info Register */
/* definitions for field: Board name in reg: Hardware Info Register */
......@@ -135,6 +147,14 @@
#define SYSC_HWIR_NAME_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SYSC_HWIR_NAME_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Storage SDBFS info */
/* definitions for field: Base address in reg: Storage SDBFS info */
#define SYSC_SDBFS_BADDR_MASK WBGEN2_GEN_MASK(0, 32)
#define SYSC_SDBFS_BADDR_SHIFT 0
#define SYSC_SDBFS_BADDR_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SYSC_SDBFS_BADDR_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Timer Control Register */
/* definitions for field: Timer Divider in reg: Timer Control Register */
......@@ -269,54 +289,56 @@
#define SYSC_REG_HWFR 0x0000000c
/* [0x10]: REG Hardware Info Register */
#define SYSC_REG_HWIR 0x00000010
/* [0x14]: REG Timer Control Register */
#define SYSC_REG_TCR 0x00000014
/* [0x18]: REG Timer Counter Value Register */
#define SYSC_REG_TVR 0x00000018
/* [0x1c]: REG User Diag: version register */
#define SYSC_REG_DIAG_INFO 0x0000001c
/* [0x20]: REG User Diag: number of words */
#define SYSC_REG_DIAG_NW 0x00000020
/* [0x24]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_CR 0x00000024
/* [0x28]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x00000028
/* [0x2c]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_CTRL 0x0000002c
/* [0x30]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_SSTAT 0x00000030
/* [0x34]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PSTAT 0x00000034
/* [0x38]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_PTPSTAT 0x00000038
/* [0x3c]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_ASTAT 0x0000003c
/* [0x40]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_TXFCNT 0x00000040
/* [0x44]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000044
/* [0x48]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_MSB 0x00000048
/* [0x4c]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x0000004c
/* [0x50]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_NS 0x00000050
/* [0x54]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000054
/* [0x58]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x00000058
/* [0x5c]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x0000005c
/* [0x60]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x00000060
/* [0x64]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000064
/* [0x68]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_CKO 0x00000068
/* [0x6c]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_SETP 0x0000006c
/* [0x70]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_UCNT 0x00000070
/* [0x74]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000074
/* [0x14]: REG Storage SDBFS info */
#define SYSC_REG_SDBFS 0x00000014
/* [0x18]: REG Timer Control Register */
#define SYSC_REG_TCR 0x00000018
/* [0x1c]: REG Timer Counter Value Register */
#define SYSC_REG_TVR 0x0000001c
/* [0x20]: REG User Diag: version register */
#define SYSC_REG_DIAG_INFO 0x00000020
/* [0x24]: REG User Diag: number of words */
#define SYSC_REG_DIAG_NW 0x00000024
/* [0x28]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_CR 0x00000028
/* [0x2c]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x0000002c
/* [0x30]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_CTRL 0x00000030
/* [0x34]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_SSTAT 0x00000034
/* [0x38]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PSTAT 0x00000038
/* [0x3c]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_PTPSTAT 0x0000003c
/* [0x40]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_ASTAT 0x00000040
/* [0x44]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_TXFCNT 0x00000044
/* [0x48]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000048
/* [0x4c]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_MSB 0x0000004c
/* [0x50]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x00000050
/* [0x54]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_NS 0x00000054
/* [0x58]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000058
/* [0x5c]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x0000005c
/* [0x60]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x00000060
/* [0x64]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x00000064
/* [0x68]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000068
/* [0x6c]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_CKO 0x0000006c
/* [0x70]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_SETP 0x00000070
/* [0x74]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_UCNT 0x00000074
/* [0x78]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000078
#endif
......@@ -61,15 +61,36 @@ void storage_init(int i2cif, int i2c_addr);
int storage_sfpdb_erase(void);
int storage_match_sfp(struct s_sfpinfo *sfp);
int storage_get_sfp(struct s_sfpinfo * sfp,
uint8_t add, uint8_t pos);
int storage_get_sfp(struct s_sfpinfo *sfp, uint8_t add, uint8_t pos);
int storage_phtrans(uint32_t * val,
uint8_t write);
int storage_phtrans(uint32_t *val, uint8_t write);
int storage_init_erase(void);
int storage_init_add(const char *args[]);
int storage_init_show(void);
int storage_init_readcmd(uint8_t *buf, uint8_t bufsize, uint8_t next);
struct storage_config {
int memtype;
int valid;
uint32_t blocksize;
uint32_t baseadr;
};
extern struct storage_config storage_cfg;
#define MEM_FLASH 0
#define MEM_EEPROM 1
#define MEM_1W_EEPROM 2
#define SDBFS_REC 5
int storage_read_hdl_cfg(void);
#ifdef CONFIG_GENSDBFS
int storage_sdbfs_erase(int mem_type, uint32_t base_adr, uint32_t blocksize,
uint8_t i2c_adr);
int storage_gensdbfs(int mem_type, uint32_t base_adr, uint32_t blocksize,
uint8_t i2c_adr);
#endif
#endif
......@@ -50,6 +50,7 @@ struct SYSCON_WB {
uint32_t GPCR; /*GPIO Clear Register */
uint32_t HWFR; /*Hardware Feature Register */
uint32_t HWIR; /*Hardware Info Register */
uint32_t SDBFS; /*Flash SDBFS Info Register */
uint32_t TCR; /*Timer Control Register */
uint32_t TVR; /*Timer Counter Value Register */
uint32_t DIAG_INFO;
......@@ -127,6 +128,7 @@ static inline int sysc_get_memsize(void)
#define HW_NAME_LENGTH 5 /* 4 letters + '\0' */
void get_hw_name(char *str);
void get_storage_info(int *memtype, uint32_t *sdbfs_baddr, uint32_t *blocksize);
#define DIAG_RW_BANK 0
#define DIAG_RO_BANK 1
......@@ -140,8 +142,8 @@ int wdiag_set_valid(int enable);
int wdiag_get_valid(void);
int wdiag_get_snapshot(void);
void wdiags_write_servo_state(int wr_mode, uint8_t servostate, uint64_t mu,
uint64_t dms, int32_t asym, int32_t cko, int32_t setp,
int32_t ucnt);
uint64_t dms, int32_t asym, int32_t cko,
int32_t setp, int32_t ucnt);
void wdiags_write_port_state(int link, int locked);
void wdiags_write_ptp_state(uint8_t ptpstate);
void wdiags_write_aux_state(uint32_t aux_states);
......
......@@ -3,14 +3,72 @@
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <string.h>
#include <errno.h>
#include "shell.h"
#include "syscon.h"
#include "hw/memlayout.h"
#include "storage.h"
/*
* args[1] - where to write sdbfs image (0 - Flash, 1 - I2C EEPROM,
* 2 - 1Wire EEPROM)
* args[2] - base address for sdbfs image in Flash/EEPROM
* args[3] - i2c address of EEPROM or blocksize of Flash
*/
static int cmd_sdb(const char *args[])
{
sdb_print_devices();
return 0;
#ifdef CONFIG_GENSDBFS
uint8_t i2c_adr = FMC_EEPROM_ADR;
int blocksize = 1;
#endif
if (!args[0]) {
sdb_print_devices();
return 0;
}
#ifdef CONFIG_GENSDBFS
if (!args[1])
return -EINVAL;
/* interpret args[3] as i2c adr or blocksize depending on memory type */
if (args[3] && atoi(args[1]) == MEM_FLASH)
blocksize = atoi(args[3])*1024;
else if (args[3])
i2c_adr = atoi(args[3]);
/* Writing SDBFS image */
if (!strcasecmp(args[0], "fs") && args[2]) {
/* if all the parameters were specified from the cmd line, we
* use these */
storage_gensdbfs(atoi(args[1]), atoi(args[2]), blocksize,
i2c_adr);
return 0;
}
if (!strcasecmp(args[0], "fs") && storage_cfg.valid &&
atoi(args[1]) == MEM_FLASH) {
/* if available, we can also use Flash parameters specified with
* HDL generics */
storage_gensdbfs(MEM_FLASH, storage_cfg.baseadr,
storage_cfg.blocksize, 0);
return 0;
}
/* Erasing SDBFS image */
if (!strcasecmp(args[0], "fse") && args[2]) {
storage_sdbfs_erase(atoi(args[1]), atoi(args[2]), blocksize,
i2c_adr);
return 0;
}
if (!strcasecmp(args[0], "fse") && storage_cfg.valid &&
atoi(args[1]) == MEM_FLASH) {
storage_sdbfs_erase(MEM_FLASH, storage_cfg.baseadr,
storage_cfg.blocksize, 0);
return 0;
}
#endif
return -EINVAL;
}
DEFINE_WRC_COMMAND(sdb) = {
......
......@@ -56,6 +56,7 @@ static void wrc_initialize(void)
timer_init(1);
get_hw_name(wrc_hw_name);
storage_read_hdl_cfg();
wrpc_w1_init();
wrpc_w1_bus.detail = ONEWIRE_PORT;
w1_scan_bus(&wrpc_w1_bus);
......@@ -69,12 +70,12 @@ static void wrc_initialize(void)
if (get_persistent_mac(ONEWIRE_PORT, mac_addr) == -1) {
pp_printf("Unable to determine MAC address\n");
mac_addr[0] = 0x22; //
mac_addr[1] = 0x33; //
mac_addr[2] = 0x44; // fallback MAC if get_persistent_mac fails
mac_addr[3] = 0x55; //
mac_addr[4] = 0x66; //
mac_addr[5] = 0x77; //
mac_addr[0] = 0x22; /*
mac_addr[1] = 0x33; *
mac_addr[2] = 0x44; * fallback MAC if get_persistent_mac fails
mac_addr[3] = 0x55; *
mac_addr[4] = 0x66; *
mac_addr[5] = 0x77; */
}
pp_printf("Local MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
......@@ -91,7 +92,7 @@ static void wrc_initialize(void)
minic_init();
shw_pps_gen_init();
wrc_ptp_init();
//try reading t24 phase transition from EEPROM
/* try reading t24 phase transition from EEPROM */
calib_t24p(WRC_MODE_MASTER, &cal_phase_transition);
spll_very_init();
usleep_init();
......@@ -227,7 +228,7 @@ static void account_task(struct wrc_task *t, int done_sth)
delta += 1000 * 1000 * 1000;
t->nanos += delta;
if (t-> nanos > 1000 * 1000 * 1000) {
if (t->nanos > 1000 * 1000 * 1000) {
t->nanos -= 1000 * 1000 * 1000;
t->seconds++;
}
......
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