doc: update documentation for sdbfs generation shell command

93b93b2f · Grzegorz Daniluk · Adam Wujek · aa9161b7 · 93b93b2f · 93b93b2f
Commit 93b93b2f authored Nov 28, 2017 by Grzegorz Daniluk Committed by Adam Wujek Nov 29, 2017
Showing with 48 additions and 3 deletions

wrc_board.tex doc/HDLdoc/wrc_board.tex +6 -0

wrc_generics.tex doc/HDLdoc/wrc_generics.tex +11 -0

wrc_ports.tex doc/HDLdoc/wrc_ports.tex +3 -3

wrpc.tex doc/wrpc.tex +28 -0

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--- a/doc/HDLdoc/wrc_board.tex
+++ b/doc/HDLdoc/wrc_board.tex
@@ -66,6 +66,12 @@ their own BSP, can find the board-common module under:
  \cline{1-3}
  g\_with\_external\_clock\_input & boolean & true & \\
  \cline{1-3}
+  g\_board\_name & string & "NA   " & \\
+  \cline{1-3}
+  g\_flash\_secsz\_kb & integer & 256 & \\
+  \cline{1-3}
+  g\_flash\_sdbfs\_baddr & integer & 0x600000 & \\
+  \cline{1-3}
  g\_aux\_clks & integer & 0 & \\
  \cline{1-3}
  g\_dpram\_initf & string & "" & \\

--- a/doc/HDLdoc/wrc_generics.tex
+++ b/doc/HDLdoc/wrc_generics.tex
@@ -8,6 +8,17 @@
  g\_with\_external\_clock\_input & boolean & false &
  enable external clock and 1-PPS inputs. The PLL inside WRPC will lock to
  external 10 MHz and 1-PPS signal when operating in GrandMaster mode\\
+  \hline
+  g\_board\_name & string & "NA  " & board name, exported by WRPC software as
+  SNMP object for diagnostics\\
+  \hline
+  g\_flash\_secsz\_kb & integer & 256 & Flash memory sector size in kilobytes.
+  Available through a Wishbone register, used by WRPC software to read/write
+  SDBFS image\\
+  \hline
+  g\_flash\_sdbfs\_baddr & integer & 0x600000 & Default base address in Flash
+  memory where \code{sdb fs} command should store an empty SDBFS image\\
+  \hline
  g\_phys\_uart & boolean & true & enable physical UART interface\\
  \hline
  g\_virtual\_uart & boolean & false & enable virtual UART interface\\

--- a/doc/HDLdoc/wrc_ports.tex
+++ b/doc/HDLdoc/wrc_ports.tex
@@ -29,7 +29,7 @@
  \hline
  rst\_n\_i & in & 1 & main reset input, active-low (hold for at least 5
  \tts{clk\_sys\_i} cycles)\\
-  \hline
+  \hline\pagebreak
  \hdltablesection{Timing system}\\
  \hline
  dac\_hpll\_load\_p1\_o & out & 1 & validates DAC value on data port \\
@@ -89,7 +89,7 @@
    when \tts{g\_pcs\_16bit = true}}\\
  \cline{1-3}
  phy16\_i & in & rec & \\
-  \hline
+  \hline\pagebreak
  \hdltablesection{GPIO}\\
  \hline
  led\_act\_o & out & 1 & signal for driving Ethernet activity LED\\
@@ -103,7 +103,7 @@
  scl\_i & in  & 1 & \\
  \cline{1-3}
  scl\_o & out & 1 & \\
-  \hline\pagebreak
+  \hline
  sfp\_sda\_i & in  & 1 & \multirowpar{4}{I2C interface for EEPROM inside SFP module}\\
  \cline{1-3}
  sfp\_sda\_o & out & 1 & \\

--- a/doc/wrpc.tex
+++ b/doc/wrpc.tex
@@ -1849,6 +1849,34 @@ tools used to build and run it, you can write to our mailing list

  \code{sdb} & prints devices connected to the Wishbone bus inside WRPC \\

+  \code{sdb fs <memtype> <baseadr> <param>} & creates SDBFS image under
+    specified \code{<baseadr>} in selected storage depending on \code{<memtype>}
+    ({\bf 0} - Flash, {\bf 1} - I2C EEPROM, {\bf 2} - 1-Wire EEPROM). The meaning
+    of last parameter \code{<param>} depends on the type of selected storage. It
+    is either the sector size in kilobytes (for Flash) or I2C chip address (for
+    I2C EEPROM). Command \code{sdb} is available if \texttt{CONFIG\_GENSDBFS}
+    is set.\\
+
+  \code{sdb fs 0} & creates SDBFS image in Flash memory. Base address and sector
+    size are taken from HDL Syscon registers for SPEC/SVEC boards. If you want
+    to use it for custom board, base address and sector size must be specified
+    as VHDL generic parameters of the WR PTP Core. Command \code{sdb} is
+    available if \texttt{CONFIG\_GENSDBFS} is set.\\
+
+  \code{sdb fse <memtype> <baseadr> <param>} & erases SDBFS image under
+    specified \code{<baseadr>} from selected storage depending on
+    \code{<memtype>} ({\bf 0} - Flash, {\bf 1} - I2C EEPROM, {\bf 2} - 1-Wire
+    EEPROM). The meaning of last parameter \code{<param>} depends on the type
+    of selected storage. It is either the sector size in kilobytes (for Flash)
+    or I2C chip address (for I2C EEPROM). Command \code{sdb} is available
+    if \texttt{CONFIG\_GENSDBFS} is set.\\
+
+  \code{sdb fse 0} & erases SDBFS image from Flash memory. Base address and sector
+    size are taken from HDL Syscon registers for SPEC/SVEC boards. If you want
+    to use it for custom board, base address and sector size must be specified
+    as VHDL generic parameters of the WR PTP Core. Command \code{sdb} is
+    available if \texttt{CONFIG\_GENSDBFS} is set.\\
+
  \code{sfp add <PN> <deltaTx> <deltaRx> <alpha>} & stores calibration
    parameters for SFP to a file in Flash/EEPROM \\