Added spec7_ad9516_init

95071540 · Peter Jansweijer · 50f1c0e7 · 95071540 · 95071540 · 95071540
Commit 95071540 authored Oct 02, 2019 by Peter Jansweijer
8 changed files
--- a/dev/ad9516.c
+++ b/dev/ad9516.c
@@ -19,7 +19,11 @@

 #include "board.h"
 #include "syscon.h"
+
+#ifdef CONFIG_WR_NODE
+#else /* CONFIG_WR_SWITCH */
 #include "gpio-wrs.h"
+#endif

 #include "rt_ipc.h"

@@ -216,6 +220,36 @@ static void ad9516_sync_outputs(void *spi_base)

 }

+#ifdef CONFIG_WR_NODE
+
+int spec7_ad9516_init(void)
+{
+	pp_printf("Initializing SPEC7 AD9516 PLL...\n");
+
+	oc_spi_init((void *)BASE_SPI);
+	
+	void *spi_base = (void *)BASE_SPI;
+
+	/* reset the PLL */
+	gpio_out(GPIO_PLL_RESET, 1);
+	timer_delay(10);
+	gpio_out(GPIO_PLL_RESET, 0);
+	timer_delay(10);
+	
+	/* Use unidirectional SPI mode */
+	ad9516_write_reg(spi_base, 0x000, 0x99);
+
+	/* Check the presence of the chip */
+	if (ad9516_read_reg(spi_base, 0x3) != 0x43) {
+		pp_printf("Error: AD9516 PLL not responding.\n");
+		return -1;
+	}
+
+  ad9516_load_regset(spi_base, ad9516_base_config_spec7, ARRAY_SIZE(ad9516_base_config_spec7), 0);
+}
+
+#else /* CONFIG_WR_SWITCH */
+
 int ad9516_init(int scb_version, int ljd_present)
 {
 	pp_printf("Initializing AD9516 PLL...\n");
@@ -227,9 +261,9 @@ int ad9516_init(int scb_version, int ljd_present)
 	gpio_out(GPIO_SYS_CLK_SEL, 0); /* switch to the standby reference clock, since the PLL is off after reset */

 	/* reset the PLL */
-	gpio_out(GPIO_PLL_RESET_N, 0);
+	gpio_out(GPIO_PLL_RESET, 1);
 	timer_delay(10);
-	gpio_out(GPIO_PLL_RESET_N, 1);
+	gpio_out(GPIO_PLL_RESET, 0);
 	timer_delay(10);
 	
 	/* Use unidirectional SPI mode */
@@ -317,6 +351,7 @@ int ljd_ad9516_init (void) {
 	return 0;
 }

+#endif

 int rts_debug_command(int command, int value)
 {

--- a/dev/ad9516_config.h
+++ b/dev/ad9516_config.h
@@ -218,6 +218,79 @@ const struct ad9516_reg ad9516_ljd_base_config[] = {
 {0x0231, 0x00},
 };

+
+/* Configuration for the SPEC7: Forward 125 MHz VCXO_REFCLK at CLK input to outputs 0, 1, 2 */
+const struct ad9516_reg ad9516_base_config_spec7[] = {
+{0x0000, 0x99}, /* Bidirectional */
+{0x0001, 0x00},
+{0x0002, 0x50},
+{0x0003, 0x43},
+{0x0004, 0x00},
+{0x0010, 0x7D}, /* PLL Power Down */
+{0x0011, 0x01},
+{0x0012, 0x00},
+{0x0013, 0x00},
+{0x0014, 0x03},
+{0x0015, 0x00},
+{0x0016, 0x06},
+{0x0017, 0x00},
+{0x0018, 0x07},
+{0x0019, 0x00},
+{0x001A, 0x00},
+{0x001B, 0x00},
+{0x001C, 0x00},
+{0x001D, 0x00},
+{0x001E, 0x00},
+{0x001F, 0x0E},
+{0x00A0, 0x01},
+{0x00A1, 0x00},
+{0x00A2, 0x00},
+{0x00A3, 0x01},
+{0x00A4, 0x00},
+{0x00A5, 0x00},
+{0x00A6, 0x01},
+{0x00A7, 0x00},
+{0x00A8, 0x00},
+{0x00A9, 0x01},
+{0x00AA, 0x00},
+{0x00AB, 0x00},
+{0x00F0, 0x08}, /* OUT0 LVDS Default, Normal Operation */
+{0x00F1, 0x08}, /* OUT1 LVDS Default, Normal Operation */
+{0x00F2, 0x08}, /* OUT2 LVDS Default, Normal Operation */
+{0x00F3, 0x0B}, /* OUT3 Total Power Down */
+{0x00F4, 0x0B}, /* OUT4 Total Power Down */
+{0x00F5, 0x0B}, /* OUT5 Total Power Down */
+{0x0140, 0x43}, /* OUT6 Power Off */
+{0x0141, 0x43}, /* OUT7 Power Off */
+{0x0142, 0x43}, /* OUT8 Power Off */
+{0x0143, 0x43}, /* OUT9 Power Off */
+{0x0190, 0x00},
+{0x0191, 0x80},
+{0x0192, 0x02},
+{0x0193, 0xBB},
+{0x0194, 0x80},
+{0x0195, 0x02},
+{0x0196, 0x00},
+{0x0197, 0x00},
+{0x0198, 0x00},
+{0x0199, 0x22},
+{0x019A, 0x00},
+{0x019B, 0x11},
+{0x019C, 0x00},
+{0x019D, 0x00},
+{0x019E, 0x22},
+{0x019F, 0x00},
+{0x01A0, 0x11},
+{0x01A1, 0x00},
+{0x01A2, 0x00},
+{0x01A3, 0x00},
+{0x01E0, 0x02},
+{0x01E1, 0x00}, /* CLK is routed directly */
+{0x0230, 0x00},
+{0x0231, 0x00},
+{0x0232, 0x01}  /* update registers! */
+};
+
 /* Config for 25 MHz VCTCXO reference (RDiv = 5, use REF1) */
 const struct ad9516_reg ad9516_ref_tcxo[] = {
 {0x0011, 0x05},

--- a/dev/dev.mk
+++ b/dev/dev.mk
@@ -4,6 +4,7 @@
 obj-$(CONFIG_LM32) += dev/uart.o

 obj-$(CONFIG_EMBEDDED_NODE) += \
+	dev/ad9516.o \
 	dev/endpoint.o \
 	dev/ep_pfilter.o \
 	dev/i2c.o \

--- a/include/board-wrc.h
+++ b/include/board-wrc.h
@@ -52,6 +52,8 @@ int board_update(void);
 #define BOARD_MAX_CHAN_AUX		2
 #define BOARD_MAX_PTRACKERS		1

+#define BASE_SPI 0x20900
+
 #ifdef CONFIG_IP
 #define HAS_IP 1
 #else

--- a/include/hw/wrc_syscon_regs.h
+++ b/include/hw/wrc_syscon_regs.h
@@ -3,7 +3,7 @@

  * File           : wrc_syscon_regs.h
  * Author         : auto-generated by wbgen2 from wrc_syscon_wb.wb
-  * Created        : Mon Nov 27 13:37:56 2017
+  * Created        : 10/30/19 09:08:37
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
@@ -14,11 +14,7 @@
 #ifndef __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB
 #define __WBGEN2_REGDEFS_WRC_SYSCON_WB_WB

-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
 #include <inttypes.h>
-#endif

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))
@@ -90,6 +86,15 @@
 /* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
 #define SYSC_GPSR_SPI_MISO                    WBGEN2_GEN_MASK(13, 1)

+/* definitions for field: PLL_RESET in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_PLL_RESET                   WBGEN2_GEN_MASK(14, 1)
+
+/* definitions for field: PLL_LOCK in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_PLL_LOCK                    WBGEN2_GEN_MASK(15, 1)
+
+/* definitions for field: PLL_STATUS in reg: GPIO Set/Readback Register */
+#define SYSC_GPSR_PLL_STATUS                  WBGEN2_GEN_MASK(16, 1)
+
 /* definitions for register: GPIO Clear Register */

 /* definitions for field: Status LED in reg: GPIO Clear Register */
@@ -119,6 +124,9 @@
 /* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
 #define SYSC_GPCR_SPI_MOSI                    WBGEN2_GEN_MASK(12, 1)

+/* definitions for field: PLL_RESET in reg: GPIO Clear Register */
+#define SYSC_GPCR_PLL_RESET                   WBGEN2_GEN_MASK(14, 1)
+
 /* definitions for register: Hardware Feature Register */

 /* definitions for field: Memory size in reg: Hardware Feature Register */

--- a/include/syscon.h
+++ b/include/syscon.h
@@ -88,6 +88,9 @@ struct SYSCON_WB {
 #define GPIO_SPI_NCS      SYSC_GPSR_SPI_NCS
 #define GPIO_SPI_MOSI     SYSC_GPSR_SPI_MOSI
 #define GPIO_SPI_MISO     SYSC_GPSR_SPI_MISO
+#define GPIO_PLL_RESET    SYSC_GPSR_PLL_RESET
+#define GPIO_PLL_LOCK     SYSC_GPSR_PLL_LOCK
+#define GPIO_PLL_STATUS   SYSC_GPSR_PLL_STATUS

 #define WRPC_FMC_I2C  0
 #define WRPC_SFP_I2C  1

--- a/include/wrc.h
+++ b/include/wrc.h
@@ -71,6 +71,7 @@ extern int wrc_ui_refperiod;

 /* Init functions and defaults for the wrs build */
 int ad9516_init(int scb_ver, int ljd_present);
+int spec7_ad9516_init(void);
 int ljd_ad9516_init(void);
 void rts_init(void);
 int rtipc_init(void);

--- a/wrc_main.c
+++ b/wrc_main.c
@@ -92,6 +92,7 @@ static void wrc_initialize(void)
 		mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
 		mac_addr[4], mac_addr[5]);

+	spec7_ad9516_init();
 	net_rst();
 	ep_init(mac_addr);
 	/* Sleep for 1s to make sure WRS v4.2 always realizes that