Commit c71b62e1 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

modify ad9516 settings to clean-up aux clock (10MHz) generated from FPGA

parent 7e2ee9b4
......@@ -246,11 +246,10 @@ int ad9516_init(int scb_version)
if( scb_version >= 34) { //New SCB v3.4. 10MHz Output.
ad9516_set_output_divider(2, 4, 0); // OUT2. 187.5 MHz.
ad9516_set_output_divider(3, 4, 0); // OUT3. 187.5 MHz.
ad9516_set_output_divider(2, 4, 0); // OUT2. 187.5 MHz. - not anymore
ad9516_set_output_divider(3, 4, 0); // OUT3. 187.5 MHz. - not anymore
ad9516_set_output_divider(4, 3, 0); // OUT4. 250 MHz.
ad9516_set_output_divider(5, 3, 0); // OUT5. 250 MHz.
ad9516_set_output_divider(4, 1, 0); // OUT4. 500 MHz.
/*The following PLL outputs have been configured through the ad9516_base_config_34 register,
* so it doesn't need to replicate the configuration:
......@@ -264,13 +263,13 @@ int ad9516_init(int scb_version)
} else { //Old one
ad9516_set_output_divider(9, 4, 0); /* AUX/SWCore = 187.5 MHz */
ad9516_set_output_divider(7, 12, 0); /* REF = 62.5 MHz */
ad9516_set_output_divider(4, 12, 0); /* GTX = 62.5 MHz */
ad9516_set_output_divider(9, 4, 0); /* AUX/SWCore = 187.5 MHz */ //not needed anymore
ad9516_set_output_divider(7, 8, 0); /* REF = 62.5 MHz */
ad9516_set_output_divider(4, 8, 0); /* GTX = 62.5 MHz */
}
ad9516_sync_outputs();
ad9516_set_vco_divider(2);
ad9516_set_vco_divider(3);
TRACE("AD9516 locked.\n");
......
......@@ -125,7 +125,7 @@ const struct ad9516_reg ad9516_base_config_34[] = {
{0x0196, 0x10},
{0x0197, 0x00},
{0x0198, 0x00},
{0x0199, 0x55},
{0x0199, 0x33},
{0x019A, 0x00},
{0x019B, 0x11},
{0x019C, 0x20},
......
......@@ -53,7 +53,7 @@ void update_rx_queues(void);
/* refresh period for _gui_ and _stat_ commands */
extern int wrc_ui_refperiod;
/* Init functions for the wrs build */
/* Init functions and defaults for the wrs build */
int ad9516_init(int scb_ver);
void rts_init(void);
int rtipc_init(void);
......
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