Commit c9b5aafe authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana Committed by Grzegorz Daniluk

added flash interface files

parent 6eeacee1
...@@ -7,7 +7,8 @@ obj-$(CONFIG_WR_NODE) += \ ...@@ -7,7 +7,8 @@ obj-$(CONFIG_WR_NODE) += \
dev/syscon.o \ dev/syscon.o \
dev/sfp.o \ dev/sfp.o \
dev/devicelist.o \ dev/devicelist.o \
dev/rxts_calibrator.o dev/rxts_calibrator.o \
dev/flash.o
obj-$(CONFIG_WR_SWITCH) += dev/timer-wrs.o dev/ad9516.o obj-$(CONFIG_WR_SWITCH) += dev/timer-wrs.o dev/ad9516.o
......
/*
*==============================================================================
* CERN (BE-CO-HT)
* Source file for M25P flash controller
*==============================================================================
*
* author: Theodor Stana (t.stana@cern.ch)
*
* date of creation: 2013-09-25
*
* version: 1.0
*
* description:
*
* dependencies:
*
* references:
*
*==============================================================================
* GNU LESSER GENERAL PUBLIC LICENSE
*==============================================================================
* This source file is free software; you can redistribute it and/or modify it
* under the terms of the GNU Lesser General Public License as published by the
* Free Software Foundation; either version 2.1 of the License, or (at your
* option) any later version. This source is distributed in the hope that it
* will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU Lesser General Public License for more details. You should have
* received a copy of the GNU Lesser General Public License along with this
* source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
*==============================================================================
* last changes:
* 2013-09-25 Theodor Stana t.stana@cern.ch File created
*==============================================================================
* TODO: -
*==============================================================================
*/
#include "flash.h"
#include "types.h"
#include "syscon.h"
static void delay()
{
int i;
for (i = 0; i < 1; i++)
asm volatile ("nop");
}
/*
* Bit-bang SPI transfer function
*/
static uint8_t bbspi_transfer(uint8_t cspin, uint8_t val)
{
uint8_t i, retval = 0;
gpio_out(GPIO_SPI_NCS, cspin);
for (i = 0; i < 8; i++)
{
gpio_out(GPIO_SPI_SCLK, 0);
if (val & 0x80)
{
gpio_out(GPIO_SPI_MOSI, 1);
}
else
{
gpio_out(GPIO_SPI_MOSI, 0);
}
delay();
gpio_out(GPIO_SPI_SCLK, 1);
retval <<= 1;
retval |= gpio_in(GPIO_SPI_MISO);
delay();
val <<= 1;
}
gpio_out(GPIO_SPI_SCLK, 0);
return retval;
}
void flash_init()
{
gpio_out(GPIO_SPI_NCS, 1);
gpio_out(GPIO_SPI_SCLK, 0);
gpio_out(GPIO_SPI_MOSI, 0);
}
void flash_write(int nrbytes, uint32_t addr, uint8_t *dat)
{
int i;
bbspi_transfer(1,0);
bbspi_transfer(0,0x06);
bbspi_transfer(1,0);
bbspi_transfer(0,0x02);
bbspi_transfer(0,(addr & 0xFF0000) >> 16);
bbspi_transfer(0,(addr & 0xFF00) >> 8);
bbspi_transfer(0,(addr & 0xFF));
for ( i = 0; i < nrbytes; i++ )
{
bbspi_transfer(0,dat[i]);
}
bbspi_transfer(1,0);
}
void flash_read(int nrbytes, uint32_t addr, uint8_t *dat)
{
int cnt = 0;
int i;
// d = 1;
bbspi_transfer(1,0);
// mprintf("cmd\n");
bbspi_transfer(0,0x0b);
// mprintf("addr0\n");
bbspi_transfer(0,(addr & 0xFF0000) >> 16);
// mprintf("addr1\n");
bbspi_transfer(0,(addr & 0xFF00) >> 8);
// mprintf("addr2\n");
bbspi_transfer(0,(addr & 0xFF));
bbspi_transfer(0,0);
for ( i = 0; i < nrbytes; i++ )
{
dat[i] = bbspi_transfer(0, 0);
}
bbspi_transfer(1,0);
}
void flash_serase(uint32_t addr)
{
bbspi_transfer(1,0);
bbspi_transfer(0,0x06);
bbspi_transfer(1,0);
bbspi_transfer(0,0xD8);
bbspi_transfer(0,(addr & 0xFF0000) >> 16);
bbspi_transfer(0,(addr & 0xFF00) >> 8);
bbspi_transfer(0,(addr & 0xFF));
bbspi_transfer(1,0);
}
uint8_t flash_rsr()
{
uint8_t retval;
bbspi_transfer(1,0);
bbspi_transfer(0,0x05);
retval = bbspi_transfer(0,0);
bbspi_transfer(1,0);
return retval;
}
/*
*==============================================================================
* CERN (BE-CO-HT)
* Header file for M25P flash memory controller
*==============================================================================
*
* author: Theodor Stana (t.stana@cern.ch)
*
* date of creation: 2013-09-25
*
* version: 1.0
*
* description:
*
* dependencies:
*
* references:
*
*==============================================================================
* GNU LESSER GENERAL PUBLIC LICENSE
*==============================================================================
* This source file is free software; you can redistribute it and/or modify it
* under the terms of the GNU Lesser General Public License as published by the
* Free Software Foundation; either version 2.1 of the License, or (at your
* option) any later version. This source is distributed in the hope that it
* will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU Lesser General Public License for more details. You should have
* received a copy of the GNU Lesser General Public License along with this
* source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
*==============================================================================
* last changes:
* 2013-09-25 Theodor Stana t.stana@cern.ch File created
*==============================================================================
* TODO: -
*==============================================================================
*/
#ifndef __FLASH_H_
#define __FLASH_H_
#include "types.h"
void flash_init();
void flash_write(int nrbytes, uint32_t addr, uint8_t *dat);
void flash_read(int nrbytes, uint32_t addr, uint8_t *dat);
void flash_serase(uint32_t addr);
uint8_t flash_rsr();
#endif // __FLASH_H_
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h * File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb * Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Fri Feb 17 10:20:14 2012 * Created : Wed Sep 25 14:35:39 2013
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...@@ -74,6 +74,18 @@ ...@@ -74,6 +74,18 @@
/* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */ /* definitions for field: SFP I2C bitbanged SDA in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SFP_SDA WBGEN2_GEN_MASK(9, 1) #define SYSC_GPSR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
/* definitions for field: SPI bitbanged NCS in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_NCS WBGEN2_GEN_MASK(11, 1)
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MISO WBGEN2_GEN_MASK(13, 1)
/* definitions for register: GPIO Clear Register */ /* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */ /* definitions for field: Status LED in reg: GPIO Clear Register */
...@@ -94,6 +106,15 @@ ...@@ -94,6 +106,15 @@
/* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */ /* definitions for field: FMC I2C bitbanged SDA in reg: GPIO Clear Register */
#define SYSC_GPCR_SFP_SDA WBGEN2_GEN_MASK(9, 1) #define SYSC_GPCR_SFP_SDA WBGEN2_GEN_MASK(9, 1)
/* definitions for field: SPI bitbanged SCLK in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_SCLK WBGEN2_GEN_MASK(10, 1)
/* definitions for field: SPI bitbanged CS in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_CS WBGEN2_GEN_MASK(11, 1)
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
/* definitions for register: Hardware Feature Register */ /* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */ /* definitions for field: Memory size in reg: Hardware Feature Register */
......
...@@ -45,6 +45,10 @@ struct SYSCON_WB { ...@@ -45,6 +45,10 @@ struct SYSCON_WB {
#define GPIO_BTN1 SYSC_GPSR_BTN1 #define GPIO_BTN1 SYSC_GPSR_BTN1
#define GPIO_BTN2 SYSC_GPSR_BTN2 #define GPIO_BTN2 SYSC_GPSR_BTN2
#define GPIO_SFP_DET SYSC_GPSR_SFP_DET #define GPIO_SFP_DET SYSC_GPSR_SFP_DET
#define GPIO_SPI_SCLK SYSC_GPSR_SPI_SCLK
#define GPIO_SPI_NCS SYSC_GPSR_SPI_NCS
#define GPIO_SPI_MOSI SYSC_GPSR_SPI_MOSI
#define GPIO_SPI_MISO SYSC_GPSR_SPI_MISO
#define WRPC_FMC_I2C 0 #define WRPC_FMC_I2C 0
#define WRPC_SFP_I2C 1 #define WRPC_SFP_I2C 1
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include "shell.h" #include "shell.h"
#include "lib/ipv4.h" #include "lib/ipv4.h"
#include "rxts_calibrator.h" #include "rxts_calibrator.h"
#include "flash.h"
#include "wrc_ptp.h" #include "wrc_ptp.h"
...@@ -224,13 +225,54 @@ static void check_reset(void) {} ...@@ -224,13 +225,54 @@ static void check_reset(void) {}
#endif #endif
void w()
{
uint64_t i;
for (i=0;i<1024*1024*1000;i++)
asm volatile ("nop");
}
int main(void) int main(void)
{ {
uint8_t rdat[256];
int i;
check_reset(); check_reset();
wrc_ui_mode = UI_SHELL_MODE; wrc_ui_mode = UI_SHELL_MODE;
_endram = ENDRAM_MAGIC; _endram = ENDRAM_MAGIC;
sdb_find_devices();
uart_init_sw();
uart_init_hw();
timer_init(0);
mprintf("preinit\n");
//w();
mprintf("flash init\n");
uint8_t d = 0xaa, r = 0x01;
flash_init();
// flash_serase(0x00);
// while (r & 0x01)
// {
// r = flash_rsr();
// mprintf("%d\n", r);
// }
// flash_write(1, 0x00, &d);
flash_read(256, 0x00, rdat);
// mprintf("0x%02x", rdat[0]);
for (i = 0; i < 256; i++)
{
mprintf("0x%02x ", rdat[i]);
}
mprintf("\n");
return 0;
wrc_initialize(); wrc_initialize();
usleep_init(); usleep_init();
shell_init(); shell_init();
......
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