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Software for White Rabbit PTP Core
Commits
ca022efb
Commit
ca022efb
authored
Mar 10, 2017
by
Grzegorz Daniluk
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hdldoc: add missing generics and ports descriptions
parent
4ea462ec
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3 changed files
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23 additions
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14 deletions
+23
-14
wrc_board.tex
doc/HDLdoc/wrc_board.tex
+7
-5
wrc_generics.tex
doc/HDLdoc/wrc_generics.tex
+11
-6
wrc_ports.tex
doc/HDLdoc/wrc_ports.tex
+5
-3
No files found.
doc/HDLdoc/wrc_board.tex
View file @
ca022efb
...
...
@@ -218,11 +218,13 @@ their own BSP, can find the board-common module under:
\hline
\hdltablesection
{
Pause frame control
}
\\
\hline
fc
\_
tx
\_
pause
\_
req
\_
i
&
in
&
1
&
\\
fc
\_
tx
\_
pause
\_
req
\_
i
&
in
&
1
&
[optional] Ethernet flow control, request sending
Pause frame
\\
\hline
fc
\_
tx
\_
pause
\_
delay
\_
i
&
in
&
16
&
\\
fc
\_
tx
\_
pause
\_
delay
\_
i
&
in
&
16
&
[optional] Pause quanta
\\
\hline
fc
\_
tx
\_
pause
\_
ready
\_
o
&
out
&
1
&
\\
fc
\_
tx
\_
pause
\_
ready
\_
o
&
out
&
1
&
[optional] Pause acknowledge - active after the
current pause send request has been completed
\\
\hline
\hdltablesection
{
WRPC timecode interface
}
\\
\hline
...
...
@@ -476,8 +478,8 @@ Parameters and ports common to all BSPs are described in Section~\ref{sec:hdl_bo
\begin{hdlparamtable}
g
\_
pcs16
\_
bit
&
boolean
&
false
&
Altera Arria V FPGAs provide the possibility
to configure the PCS of the PHY as either 8bit or 16bit. The default is to use
the 8bit PCS,
but this generic can be used to override it
\\
to configure the PCS of the PHY as either 8bit or 16bit. The default is to use
the 8bit PCS. Currently, 16bit PCS is not supported for Arria V.
\\
\end{hdlparamtable}
\subsubsection
{
Ports
}
...
...
doc/HDLdoc/wrc_generics.tex
View file @
ca022efb
...
...
@@ -17,7 +17,9 @@
g
\_
rx
\_
buffer
\_
size
&
integer
&
1024
&
size of Rx buffer in WRPC MAC module,
default value is 1024 and should not be changed
\\
\hline
g
\_
tx
\_
runt
\_
padding
&
boolean
&
true
&
\\
g
\_
tx
\_
runt
\_
padding
&
boolean
&
true
&
when set to true, all user frames
transmitted from the external fabric interface are padded if shorter than
minimal Ethernet frame size (60B with header)
\\
\hline
g
\_
dpram
\_
initf
&
string
&
""
&
filename of compiled WRPC software, to be
stored in WRPC memory during the synthesis (default is
\emph
{
wrc.ram
}
...
...
@@ -37,7 +39,9 @@
and can be left unassigned. The default value corresponds to an undocumented device with an
address space of 256 bytes
\\
\hline
g
\_
softpll
\_
enable
\_
debugger
&
boolean
&
false
&
\\
g
\_
softpll
\_
enable
\_
debugger
&
boolean
&
false
&
when set to true, additional
FIFO is instantiated in the SoftPLL for collecting DMTD tags. It can be read
out by the host and analyzed for SoftPLL debugging.
\\
\hline
g
\_
vuart
\_
fifo
\_
size
&
integer
&
1024
&
size (in bytes) for the virtual UART FIFO
\\
\hline
...
...
@@ -47,11 +51,12 @@
signals will be grouped in the
\tts
{
phy8/phy16
}
VHDL records, otherwise the individual standard
logic signals will be used
\\
\hline
g
\_
diag
\_
id
&
integer
&
0
&
\\
g
\_
diag
\_
id
&
integer
&
0
&
auxiliary diagnostics module ID
\\
\hline
g
\_
diag
\_
ver
&
integer
&
0
&
\\
g
\_
diag
\_
ver
&
integer
&
0
&
auxiliary diagnostics version for a given module ID
\\
\hline
g
\_
diag
\_
ro
\_
size
&
integer
&
0
&
\\
g
\_
diag
\_
ro
\_
size
&
integer
&
0
&
number of read-only registers fed to auxiliary diagnostics
\\
\hline
g
\_
diag
\_
rw
\_
size
&
integer
&
0
&
\\
g
\_
diag
\_
rw
\_
size
&
integer
&
0
&
number of read-write registers fed to
auxiliary diagnostics
\\
\end{hdlparamtable}
doc/HDLdoc/wrc_ports.tex
View file @
ca022efb
...
...
@@ -281,11 +281,13 @@
\hline
\hdltablesection
{
Pause frame control
}
\\
\hline
fc
\_
tx
\_
pause
\_
req
\_
i
&
in
&
1
&
\\
fc
\_
tx
\_
pause
\_
req
\_
i
&
in
&
1
&
Ethernet flow control, request sending
Pause frame
\\
\hline
fc
\_
tx
\_
pause
\_
delay
\_
i
&
in
&
16
&
\\
fc
\_
tx
\_
pause
\_
delay
\_
i
&
in
&
16
&
Pause quanta
\\
\hline
fc
\_
tx
\_
pause
\_
ready
\_
o
&
out
&
1
&
\\
fc
\_
tx
\_
pause
\_
ready
\_
o
&
out
&
1
&
Pause acknowledge - active after the
current pause send request has been completed
\\
\hline
\hdltablesection
{
Timecode/Servo control
}
\\
\hline
...
...
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