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Software for White Rabbit PTP Core
Commit cc0a65be authored by Michel Arruat's avatar Michel Arruat Committed by Adam Wujek
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hw:wr_streamers.h New streamer register mapping. 

        For naming consistency, file has been renamed.
Signed-off-by: Michel Arruat's avatarMichel Arruat <michel.arruat@cern.ch>
parent 7558f78c
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Showing with 133 additions and 73 deletions
include/hw/wr-streamer.h → include/hw/wr_streamers.h
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......@@ -3,7 +3,7 @@
* File : ./doc/wr_streamers.h
* Author : auto-generated by wbgen2 from wr_streamers_wb.wb
* Created : Mon May 8 23:18:07 2017
* Created : Wed May 17 08:49:53 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
......@@ -63,77 +63,125 @@
#define WR_STREAMERS_SSCR2_RST_TS_TAI_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_SSCR2_RST_TS_TAI_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Statistics status and ctrl register */
/* definitions for field: Reset timestamp 8 MSB of TAI in reg: Statistics status and ctrl register */
#define WR_STREAMERS_SSCR3_RST_TS_TAI_MSB_MASK WBGEN2_GEN_MASK(0, 8)
#define WR_STREAMERS_SSCR3_RST_TS_TAI_MSB_SHIFT 0
#define WR_STREAMERS_SSCR3_RST_TS_TAI_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WR_STREAMERS_SSCR3_RST_TS_TAI_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX_MASK WBGEN2_GEN_MASK(0, 28)
#define WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX_SHIFT 0
#define WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN_MASK WBGEN2_GEN_MASK(0, 28)
#define WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN_SHIFT 0
#define WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: Tx statistics */
/* definitions for field: WR Streamer frame sent count (LSB) in reg: Tx statistics */
#define WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB_SHIFT 0
#define WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Tx statistics */
/* definitions for field: WR Streamer frame sent count in reg: Tx statistics */
#define WR_STREAMERS_TX_STAT_TX_SENT_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_TX_STAT_TX_SENT_CNT_SHIFT 0
#define WR_STREAMERS_TX_STAT_TX_SENT_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_TX_STAT_TX_SENT_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: WR Streamer frame sent count (MSB) in reg: Tx statistics */
#define WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB_SHIFT 0
#define WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame received count in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT1_RX_RCVD_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT1_RX_RCVD_CNT_SHIFT 0
#define WR_STREAMERS_RX_STAT1_RX_RCVD_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT1_RX_RCVD_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: WR Streamer frame received count (LSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB_SHIFT 0
#define WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame loss count in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT2_RX_LOSS_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT2_RX_LOSS_CNT_SHIFT 0
#define WR_STREAMERS_RX_STAT2_RX_LOSS_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT2_RX_LOSS_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: WR Streamer frame received count (MSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB_SHIFT 0
#define WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT3_RX_LATENCY_MAX_MASK WBGEN2_GEN_MASK(0, 28)
#define WR_STREAMERS_RX_STAT3_RX_LATENCY_MAX_SHIFT 0
#define WR_STREAMERS_RX_STAT3_RX_LATENCY_MAX_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define WR_STREAMERS_RX_STAT3_RX_LATENCY_MAX_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: WR Streamer frame loss count (LSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB_SHIFT 0
#define WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT4_RX_LATENCY_MIN_MASK WBGEN2_GEN_MASK(0, 28)
#define WR_STREAMERS_RX_STAT4_RX_LATENCY_MIN_SHIFT 0
#define WR_STREAMERS_RX_STAT4_RX_LATENCY_MIN_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define WR_STREAMERS_RX_STAT4_RX_LATENCY_MIN_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: WR Streamer frame loss count (MSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB_SHIFT 0
#define WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT5_RX_LATENCY_ACC_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT5_RX_LATENCY_ACC_LSB_SHIFT 0
#define WR_STREAMERS_RX_STAT5_RX_LATENCY_ACC_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT5_RX_LATENCY_ACC_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: WR Streamer block loss count (LSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB_SHIFT 0
#define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT6_RX_LATENCY_ACC_MSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT6_RX_LATENCY_ACC_MSB_SHIFT 0
#define WR_STREAMERS_RX_STAT6_RX_LATENCY_ACC_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT6_RX_LATENCY_ACC_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: WR Streamer block loss count (MSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB_SHIFT 0
#define WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency counter in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT7_RX_LATENCY_ACC_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT7_RX_LATENCY_ACC_CNT_SHIFT 0
#define WR_STREAMERS_RX_STAT7_RX_LATENCY_ACC_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT7_RX_LATENCY_ACC_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: WR Streamer frame latency (LSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB_SHIFT 0
#define WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer block loss count in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_SHIFT 0
#define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: WR Streamer frame latency (MSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB_SHIFT 0
#define WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency counter (LSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB_SHIFT 0
#define WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx statistics */
/* definitions for field: WR Streamer frame latency counter (MSB) in reg: Rx statistics */
#define WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB_SHIFT 0
#define WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Tx Config Reg 0 */
......@@ -304,55 +352,67 @@ PACKED struct WR_STREAMERS_WB {
uint32_t SSCR1;
/* [0x4]: REG Statistics status and ctrl register */
uint32_t SSCR2;
/* [0x8]: REG Tx statistics */
uint32_t TX_STAT;
/* [0x8]: REG Statistics status and ctrl register */
uint32_t SSCR3;
/* [0xc]: REG Rx statistics */
uint32_t RX_STAT1;
uint32_t RX_STAT0;
/* [0x10]: REG Rx statistics */
uint32_t RX_STAT2;
/* [0x14]: REG Rx statistics */
uint32_t RX_STAT3;
/* [0x18]: REG Rx statistics */
uint32_t RX_STAT4;
uint32_t RX_STAT1;
/* [0x14]: REG Tx statistics */
uint32_t TX_STAT2;
/* [0x18]: REG Tx statistics */
uint32_t TX_STAT3;
/* [0x1c]: REG Rx statistics */
uint32_t RX_STAT5;
uint32_t RX_STAT4;
/* [0x20]: REG Rx statistics */
uint32_t RX_STAT6;
uint32_t RX_STAT5;
/* [0x24]: REG Rx statistics */
uint32_t RX_STAT7;
uint32_t RX_STAT6;
/* [0x28]: REG Rx statistics */
uint32_t RX_STAT7;
/* [0x2c]: REG Rx statistics */
uint32_t RX_STAT8;
/* [0x2c]: REG Tx Config Reg 0 */
/* [0x30]: REG Rx statistics */
uint32_t RX_STAT9;
/* [0x34]: REG Rx statistics */
uint32_t RX_STAT10;
/* [0x38]: REG Rx statistics */
uint32_t RX_STAT11;
/* [0x3c]: REG Rx statistics */
uint32_t RX_STAT12;
/* [0x40]: REG Rx statistics */
uint32_t RX_STAT13;
/* [0x44]: REG Tx Config Reg 0 */
uint32_t TX_CFG0;
/* [0x30]: REG Tx Config Reg 1 */
/* [0x48]: REG Tx Config Reg 1 */
uint32_t TX_CFG1;
/* [0x34]: REG Tx Config Reg 2 */
/* [0x4c]: REG Tx Config Reg 2 */
uint32_t TX_CFG2;
/* [0x38]: REG Tx Config Reg 3 */
/* [0x50]: REG Tx Config Reg 3 */
uint32_t TX_CFG3;
/* [0x3c]: REG Tx Config Reg 4 */
/* [0x54]: REG Tx Config Reg 4 */
uint32_t TX_CFG4;
/* [0x40]: REG Tx Config Reg 4 */
/* [0x58]: REG Tx Config Reg 4 */
uint32_t TX_CFG5;
/* [0x44]: REG Rx Config Reg 0 */
/* [0x5c]: REG Rx Config Reg 0 */
uint32_t RX_CFG0;
/* [0x48]: REG Rx Config Reg 1 */
/* [0x60]: REG Rx Config Reg 1 */
uint32_t RX_CFG1;
/* [0x4c]: REG Rx Config Reg 2 */
/* [0x64]: REG Rx Config Reg 2 */
uint32_t RX_CFG2;
/* [0x50]: REG Rx Config Reg 3 */
/* [0x68]: REG Rx Config Reg 3 */
uint32_t RX_CFG3;
/* [0x54]: REG Rx Config Reg 4 */
/* [0x6c]: REG Rx Config Reg 4 */
uint32_t RX_CFG4;
/* [0x58]: REG Rx Config Reg 5 */
/* [0x70]: REG Rx Config Reg 5 */
uint32_t RX_CFG5;
/* [0x5c]: REG TxRx Config Override */
/* [0x74]: REG TxRx Config Override */
uint32_t CFG;
/* [0x60]: REG DBG Control register */
/* [0x78]: REG DBG Control register */
uint32_t DBG_CTRL;
/* [0x64]: REG DBG Data */
/* [0x7c]: REG DBG Data */
uint32_t DBG_DATA;
/* [0x68]: REG Test value */
/* [0x80]: REG Test value */
uint32_t DUMMY;
};
......
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