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Software for White Rabbit PTP Core
Commits
f2edd0bc
Commit
f2edd0bc
authored
Mar 13, 2017
by
Grzegorz Daniluk
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doc: fix pagebreaks
parent
791d67d8
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3 changed files
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11 additions
and
12 deletions
+11
-12
wrc_board.tex
doc/HDLdoc/wrc_board.tex
+4
-4
wrc_platform.tex
doc/HDLdoc/wrc_platform.tex
+1
-2
wrc_ports.tex
doc/HDLdoc/wrc_ports.tex
+6
-6
No files found.
doc/HDLdoc/wrc_board.tex
View file @
f2edd0bc
...
...
@@ -56,6 +56,7 @@ tables short and to the point. Users interested in studying the board-common mod
their own BSP, can find the board-common module under:
\\\hrefwrpc
{
board/common/xwrc
\_
board
\_
common.vhd
}
\newpage
\newparagraph
{
Generic parameters
}
\label
{
sec:hdl
_
board
_
common
_
param
}
...
...
@@ -108,7 +109,7 @@ their own BSP, can find the board-common module under:
rst
\_
62m5
\_
n
\_
o
&
out
&
1
&
Active low reset output, synchronous to
\tts
{
clk
\_
sys
\_
62m5
\_
o
}
\\
\hline
rst
\_
125m
\_
n
\_
o
&
out
&
1
&
Active low reset output, synchronous to
\tts
{
clk
\_
ref
\_
125m
\_
o
}
\\
\hline
\hline
\pagebreak
\hdltablesection
{
Interface with SFP
}
\\
\hline
sfp
\_
tx
\_
fault
\_
i
&
in
&
1
&
TX fault indicator
\\
...
...
@@ -185,7 +186,7 @@ their own BSP, can find the board-common module under:
in order to provide access to all WB peripherals over Etherbone
}
\\
\cline
{
1-3
}
\linebreak
wb
\_
eth
\_
master
\_
i
\linebreak
&
in
&
rec
&
\\
\hline
\pagebreak
\hline
\hdltablesection
{
Generic diagnostics interface
}
\\
\hline
\linebreak
aux
\_
diag
\_
i
\linebreak
&
in
&
var
&
\multirowpar
{
2
}{
Arrays of 32~bit vectors, to be
...
...
@@ -435,7 +436,7 @@ Section~\ref{sec:hdl_board_common_param} for a the list of common BSP parameters
sfp
\_
scl
\_
o
&
out
&
1
&
\\
\hline
sfp
\_
rate
\_
select
\_
o
&
out
&
1
&
SFP rate select
\\
\hline
\pagebreak
\hline
\hdltablesection
{
Physical UART interface
}
\\
\hline
uart
\_
rxd
\_
i
&
in
&
1
&
UART RXD (serial data to WRPC)
\\
...
...
@@ -482,7 +483,6 @@ Parameters and ports common to all BSPs are described in Section~\ref{sec:hdl_bo
the 8bit PCS. Currently, 16bit PCS is not supported for Arria V.
\\
\end{hdlparamtable}
\pagebreak
\newparagraph
{
Ports
}
\begin{hdlporttable}
...
...
doc/HDLdoc/wrc_platform.tex
View file @
f2edd0bc
...
...
@@ -14,7 +14,6 @@ supported FPGAs.
This section describes the generic parameters and ports which are common to all provided PSPs.
\newpage
\newparagraph
{
Generic parameters
}
\begin{hdlparamtable}
...
...
@@ -51,7 +50,7 @@ these parameters.
\hline
clk
\_
10m
\_
ext
\_
i
&
in
&
1
&
10MHz external reference clock input
(used when
\tts
{
g
\_
with
\_
external
\_
clock
\_
input = true
}
)
\\
\hline
\hline
\pagebreak
\hdltablesection
{
Clock inputs for default PLLs (used when
\tts
{
g
\_
use
\_
default
\_
plls = true
}
)
}
\\
\hline
...
...
doc/HDLdoc/wrc_ports.tex
View file @
f2edd0bc
...
...
@@ -103,7 +103,7 @@
scl
\_
i
&
in
&
1
&
\\
\cline
{
1-3
}
scl
\_
o
&
out
&
1
&
\\
\hline
\hline
\pagebreak
sfp
\_
sda
\_
i
&
in
&
1
&
\multirowpar
{
4
}{
I2C interface for EEPROM inside SFP module
}
\\
\cline
{
1-3
}
sfp
\_
sda
\_
o
&
out
&
1
&
\\
...
...
@@ -113,7 +113,7 @@
sfp
\_
scl
\_
o
&
out
&
1
&
\\
\hline
sfp
\_
det
\_
i
&
in
&
1
&
SFP presence indicator
\\
\hline
\pagebreak
\hline
btn1
\_
i
&
in
&
1
&
\multirowpar
{
2
}{
two microswitch inputs, active low, currently not
used in official WRPC software
}
\\
\cline
{
1-3
}
...
...
@@ -173,7 +173,7 @@
for the WB slave interface (available in
\tts
{
xwr
\_
core.vhd
}
)
}
\\
\cline
{
1-3
}
wb
\_
slave
\_
i
&
in
&
rec
&
\\
\hline
\hline
\pagebreak
\hdltablesection
{
Auxiliary WB master
}
\\
\hline
aux
\_
adr
\_
i
&
in
&
32
&
\multirowpar
{
11
}{
Auxilirary Wishbone pipelined
...
...
@@ -199,7 +199,7 @@
ports for the aux WB master interface (available in
\tts
{
xwr
\_
core.vhd
}
)
}
\\
\cline
{
1-3
}
aux
\_
master
\_
i
&
in
&
rec
&
\\
\hline
\pagebreak
\hline
\hdltablesection
{
External fabric interface
}
\\
\hline
ext
\_
snk
\_
adr
\_
i
&
in
&
2
&
\multirowpar
{
9
}{
External fabric Wishbone
...
...
@@ -248,7 +248,7 @@
wrf
\_
snk
\_
o
&
out
&
rec
&
\\
\cline
{
1-3
}
wrf
\_
snk
\_
i
&
in
&
rec
&
\\
\hline
\hline
\pagebreak
\hdltablesection
{
External TX timestamp interface
}
\\
\hline
txtsu
\_
port
\_
id
\_
o
&
out
&
5
&
physical port ID from which the timestamp
...
...
@@ -271,7 +271,7 @@
\hline
txtsu
\_
ack
\_
i
&
in
&
1
&
acknowledge, indicating that user-defined module
has received the timestamp
\\
\hline
\pagebreak
\hline
\hdltablesection
{
Pause frame control
}
\\
\hline
fc
\_
tx
\_
pause
\_
req
\_
i
&
in
&
1
&
Ethernet flow control, request sending
...
...
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