Commit fd66dc57 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

boards/ertm14: imported eRTM14 board support files from tom-dev-ertm14 branch…

boards/ertm14: imported eRTM14 board support files from tom-dev-ertm14 branch and made the eRTM14 BSP
parent b4c4b73a
Pipeline #172 failed with stages
in 10 seconds
......@@ -2,3 +2,5 @@ obj-$(CONFIG_TARGET_GENERIC_PHY_8BIT) += boards/generic/board.o
obj-$(CONFIG_TARGET_GENERIC_PHY_16BIT) += boards/generic/board.o
obj-$(CONFIG_TARGET_WR_SWITCH) += boards/wr-switch/main.o boards/wr-switch/gpio-wrs.o boards/wr-switch/ad9516.o
obj-$(CONFIG_TARGET_AFCZ) += boards/afcz/board.o
obj-$(CONFIG_TARGET_ERTM14) += boards/ertm14/board.o boards/ertm14/dds_sync_unit.o boards/ertm14/ertm15_rf_distr.o boards/ertm14/phy_calibration.o
This diff is collapsed.
/*
* This work is part of the White Rabbit project
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#ifndef __BOARD_ERTM14_H
#define __BOARD_ERTM14_H
#include "dev/gpio.h"
#include "dev/bb_spi.h"
#include "dev/ad951x.h"
#include "dev/ltc6950.h"
#include "dev/ad9910.h"
#include "dev/ad9520.h"
#include "dev/clock_monitor.h"
#include "dev/24aa025.h"
#include "dev/ad7888.h"
#include "ertm15_rf_distr.h"
#include "dds_sync_unit.h"
#include "dev/spi_flash.h"
#include "dev/bb_i2c.h"
#include "dev/iuart.h"
#define BOARD_MAX_CONSOLE_DEVICES 2
/* Board-specific parameters */
#define TICS_PER_SECOND 1000
/* WR Core system/CPU clock frequency in Hz */
#define CPU_CLOCK 62500000ULL
/* WR Reference clock period (picoseconds) and frequency (Hz) */
#define REF_CLOCK_PERIOD_PS 16000
#define REF_CLOCK_FREQ_HZ 62500000
/* Center DMTD frequency (Hz) */
#define DMTD_CLOCK_FREQ_HZ 62500000
/* Baud rate of the builtin UART (does not apply to the VUART) */
#define CONSOLE_UART_BAUDRATE 921600ULL
/* Maximum number of simultaneously created sockets */
#define NET_MAX_SOCKETS 12
/* Socket buffer size, determines the max. RX packet size */
#define NET_MAX_SKBUF_SIZE 512
/* Number of auxillary clock channels - usually equal to the number of FMCs */
#define NUM_AUX_CLOCKS 1
int board_init(void);
int board_update(void);
/* spll parameter that are board-specific */
# define BOARD_DIVIDE_DMTD_CLOCKS 0
# define NS_PER_CLOCK 16
#define BOARD_MAX_CHAN_REF 1
#define BOARD_MAX_CHAN_AUX 2
#define BOARD_MAX_PTRACKERS 1
#ifdef CONFIG_IP
#define HAS_IP 1
#else
#define HAS_IP 0
#endif
#define ERTM14_MAX_CONFIGS 8
extern unsigned char *BASE_MINIC;
extern unsigned char *BASE_EP;
#define SDB_ADDRESS 0x50000
#define FMC_EEPROM_ADR 0x50
#define BASE_AUXWB 0x48000
#define BASE_SOFTPLL 0x40200
#define BASE_PPS_GEN 0x40300
#define BASE_UART 0x40500
#define BASE_SYSCON 0x40400
#define BASE_EP 0x40100
#define BASE_MINIC 0x40000
#define BASE_ONEWIRE 0x40600
#define BASE_IUART_14 (BASE_AUXWB + 0x200)
#define BASE_ERTM14_DDS_SYNC_UNIT (BASE_AUXWB + 0x300)
#define BASE_CLOCK_MONITOR (BASE_AUXWB + 0x100)
#define BASE_ERTM14_10MHZ_ALIGN_UNIT (BASE_AUXWB + 0x400)
#define ERTM14_RF_OUT_MIN_ID 4
#define ERTM14_RF_OUT_MAX_ID 12
#define ERTM14_CLKAB_OUT_MIN_ID 0
#define ERTM14_CLKAB_OUT_MAX_ID 11
// clock monitor core channels (see ertm14_top.vhd for assignment to the clock monitor core)
#define ERTM14_CMON_CLK_SYS 0
#define ERTM14_CMON_CLK_DMTD 1
#define ERTM14_CMON_CLK_PLL_FB 2
#define ERTM14_CMON_CLK_REF 3
#define ERTM14_CMON_CLK_RX 4
#define ERTM14_CLKAB_OUT_FRONT_PANEL 11
// #define ERTM14_CALIBRATION_DEBUG 1
#define ERTM14_MODE_WITHOUT_ERTM15 (1 << 0)
#define ERTM14_MODE_OCXO_10MHZ (1 << 1)
#define ERTM14_MODE_OCXO_100MHZ (1 << 2)
struct ertm14_board
{
struct gpio_device gpio_aux;
struct wb_clock_monitor_device ertm14_cmon;
struct spi_bus spi_pll_main;
struct spi_bus spi_pll_ext;
struct spi_bus spi_ltc6950;
struct spi_bus spi_ad9910_ref;
struct spi_bus spi_ad9910_lo;
struct spi_bus spi_ocxo_dac;
struct spi_bus spi_ad7888;
//struct spi_bus spi_flash;
struct i2c_bus i2c_clka_distr;
struct i2c_bus i2c_clkb_distr;
struct ad951x_device ad9516_main;
struct ad951x_device ad9516_ext;
struct ltc6950_device ltc6950_pll;
struct ad9910_device dds_ad9910_ref;
struct ad9910_device dds_ad9910_lo;
struct ad7888_device pwrmon_adc;
struct ertm15_rf_distribution_device rf_distr;
//struct spi_flash_device dev_flash;
struct ad9520_device dev_clka_distr;
struct ad9520_device dev_clkb_distr;
struct i2c_bus i2c_mac_addr;
struct m24aa025_device m24_mac_ids[2];
struct dds_sync_unit_device dds_sync_dev;
struct iuart_device iuart_14;
int mode;
};
struct ertm14_dds_config
{
uint32_t ftw;
uint8_t out_state[ERTM14_RF_OUT_MAX_ID + 1];
int out_power[ERTM14_RF_OUT_MAX_ID + 1];
int amp_power;
int ampl_factor;
};
struct ertm14_board_config
{
int valid;
struct ertm14_dds_config ref;
struct ertm14_dds_config lo;
uint32_t clka_freq_hz[ERTM14_CLKAB_OUT_MAX_ID + 1];
uint32_t clkb_freq_hz[ERTM14_CLKAB_OUT_MAX_ID + 1];
uint32_t clka_enable_mask;
uint32_t clkb_enable_mask;
};
extern struct ertm14_board board;
void ertm14_config_init(void);
struct ertm14_board_config *ertm14_get_config(int config_id);
int ertm14_apply_config(int config_id);
int ertm14_get_current_config_id(void);
int ertm14_is_config_ready(void);
int ertm14_get_clkab_divider( int freq );
#endif /* __BOARD_WRC_H */
#!/usr/bin/python
import sys
import re
n_regs = 0;
regs = []
for l in open(sys.argv[1],"rb").readlines():
r = re.match('^"(\w+)","\w+","(\w+)"', l)
if r != None:
addr = int(r.group(1), 16)
value = int(r.group(2), 16)
regs += [(addr,value)]
n_regs+=1
print("{")
print("%d," % n_regs)
print("{")
for r in regs:
print(" { 0x%02x, 0x%02x }, " % r );
print("}\n};\n")
{
68,
{
{ 0x00, 0x18 },
{ 0x01, 0x00 },
{ 0x02, 0x10 },
{ 0x03, 0xc3 },
{ 0x04, 0x00 },
{ 0x10, 0x7c },
{ 0x11, 0x01 },
{ 0x12, 0x00 },
{ 0x13, 0x06 },
{ 0x14, 0x09 },
{ 0x15, 0x00 },
{ 0x16, 0x05 },
{ 0x17, 0x00 },
{ 0x18, 0x07 },
{ 0x19, 0x00 },
{ 0x1a, 0x00 },
{ 0x1b, 0x00 },
{ 0x1c, 0x43 },
{ 0x1d, 0x00 },
{ 0x1e, 0x00 },
{ 0x1f, 0x0e },
{ 0xa0, 0x01 },
{ 0xa1, 0x00 },
{ 0xa2, 0x00 },
{ 0xa3, 0x01 },
{ 0xa4, 0x00 },
{ 0xa5, 0x00 },
{ 0xa6, 0x01 },
{ 0xa7, 0x00 },
{ 0xa8, 0x00 },
{ 0xa9, 0x01 },
{ 0xaa, 0x00 },
{ 0xab, 0x00 },
{ 0xf0, 0x0a },
{ 0xf1, 0x0a },
{ 0xf2, 0x0a },
{ 0xf3, 0x0a },
{ 0xf4, 0x0a },
{ 0xf5, 0x0a },
{ 0x140, 0x42 },
{ 0x141, 0x43 },
{ 0x142, 0x43 },
{ 0x143, 0x43 },
{ 0x190, 0x00 },
{ 0x191, 0x80 },
{ 0x192, 0x00 },
{ 0x193, 0xbb },
{ 0x194, 0x00 },
{ 0x195, 0x00 },
{ 0x196, 0x00 },
{ 0x197, 0x00 },
{ 0x198, 0x00 },
{ 0x199, 0x22 },
{ 0x19a, 0x00 },
{ 0x19b, 0x11 },
{ 0x19c, 0x20 },
{ 0x19d, 0x00 },
{ 0x19e, 0x22 },
{ 0x19f, 0x00 },
{ 0x1a0, 0x11 },
{ 0x1a1, 0x00 },
{ 0x1a2, 0x00 },
{ 0x1a3, 0x00 },
{ 0x1e0, 0x02 },
{ 0x1e1, 0x02 },
{ 0x230, 0x00 },
{ 0x231, 0x00 },
{ 0x232, 0x00 },
}
};
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111100","7C"
"0011","00000001","01"
"0012","00000000","00"
"0013","00000110","06"
"0014","00001001","09"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001000","08"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001000","08"
"0140","01000011","43"
"0141","01000010","42"
"0142","01000011","43"
"0143","01000010","42"
"0190","00100010","22"
"0191","00000000","00"
"0192","00000000","00"
"0193","00100010","22"
"0194","00000000","00"
"0195","00000000","00"
"0196","00100010","22"
"0197","00000000","00"
"0198","00000000","00"
"0199","00100010","22"
"019A","00000000","00"
"019B","00000000","00"
"019C","00100000","20"
"019D","00000000","00"
"019E","00100010","22"
"019F","00000000","00"
"01A0","00000000","00"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000000","00"
"01E1","00000010","02"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",10
"REF 2:",0
"VCO:",1500
"CLK:",1200
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",1
{
68,
{
{ 0x00, 0x18 },
{ 0x01, 0x00 },
{ 0x02, 0x10 },
{ 0x03, 0xc3 },
{ 0x04, 0x00 },
{ 0x10, 0x7c },
{ 0x11, 0x01 },
{ 0x12, 0x00 },
{ 0x13, 0x06 },
{ 0x14, 0x09 },
{ 0x15, 0x00 },
{ 0x16, 0x05 },
{ 0x17, 0x00 },
{ 0x18, 0x07 },
{ 0x19, 0x00 },
{ 0x1a, 0x00 },
{ 0x1b, 0x00 },
{ 0x1c, 0x02 },
{ 0x1d, 0x00 },
{ 0x1e, 0x00 },
{ 0x1f, 0x0e },
{ 0xa0, 0x01 },
{ 0xa1, 0x00 },
{ 0xa2, 0x00 },
{ 0xa3, 0x01 },
{ 0xa4, 0x00 },
{ 0xa5, 0x00 },
{ 0xa6, 0x01 },
{ 0xa7, 0x00 },
{ 0xa8, 0x00 },
{ 0xa9, 0x01 },
{ 0xaa, 0x00 },
{ 0xab, 0x00 },
{ 0xf0, 0x08 },
{ 0xf1, 0x0a },
{ 0xf2, 0x08 },
{ 0xf3, 0x0a },
{ 0xf4, 0x0a },
{ 0xf5, 0x08 },
{ 0x140, 0x43 },
{ 0x141, 0x42 },
{ 0x142, 0x43 },
{ 0x143, 0x42 },
{ 0x190, 0x22 },
{ 0x191, 0x00 },
{ 0x192, 0x00 },
{ 0x193, 0xff },
{ 0x194, 0x00 },
{ 0x195, 0x00 },
{ 0x196, 0x22 },
{ 0x197, 0x00 },
{ 0x198, 0x00 },
{ 0x199, 0x22 },
{ 0x19a, 0x00 },
{ 0x19b, 0x00 },
{ 0x19c, 0x00 },
{ 0x19d, 0x00 },
{ 0x19e, 0x22 },
{ 0x19f, 0x00 },
{ 0x1a0, 0x00 },
{ 0x1a1, 0x00 },
{ 0x1a2, 0x00 },
{ 0x1a3, 0x00 },
{ 0x1e0, 0x00 },
{ 0x1e1, 0x02 },
{ 0x230, 0x00 },
{ 0x231, 0x00 },
{ 0x232, 0x00 },
}
};
"AD9516 Setup File"
"Rev.","1.1.0"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00011000","18"
"0001","00000000","00"
"0002","00010000","10"
"0003","11000011","C3"
"0004","00000000","00"
"0010","01111101","7D"
"0011","00000001","01"
"0012","00000000","00"
"0013","00000110","06"
"0014","00001001","09"
"0015","00000000","00"
"0016","00000101","05"
"0017","00000000","00"
"0018","00000111","07"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","00000010","02"
"001D","00000000","00"
"001E","00000000","00"
"001F","00001110","0E"
"00A0","00000001","01"
"00A1","00000000","00"
"00A2","00000000","00"
"00A3","00000001","01"
"00A4","00000000","00"
"00A5","00000000","00"
"00A6","00000001","01"
"00A7","00000000","00"
"00A8","00000000","00"
"00A9","00000001","01"
"00AA","00000000","00"
"00AB","00000000","00"
"00F0","00001000","08"
"00F1","00001010","0A"
"00F2","00001000","08"
"00F3","00001010","0A"
"00F4","00001010","0A"
"00F5","00001000","08"
"0140","01000011","43"
"0141","01000010","42"
"0142","01000011","43"
"0143","01000010","42"
"0190","00100010","22"
"0191","10000000","80"
"0192","00000000","00"
"0193","00100010","22"
"0194","10000000","80"
"0195","00000000","00"
"0196","00100010","22"
"0197","10000000","80"
"0198","00000000","00"
"0199","00000000","00"
"019A","00000000","00"
"019B","00000000","00"
"019C","00100000","20"
"019D","00000000","00"
"019E","00000000","00"
"019F","00000000","00"
"01A0","00000000","00"
"01A1","00100000","20"
"01A2","00000000","00"
"01A3","00000000","00"
"01E0","00000000","00"
"01E1","00000001","01"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"","",""
"Other Settings..."
"REF 1:",10
"REF 2:",0
"VCO:",1500
"CLK:",125
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",1
{
68,
{
{ 0x00, 0x18 },
{ 0x01, 0x00 },
{ 0x02, 0x10 },
{ 0x03, 0xc3 },
{ 0x04, 0x00 },
{ 0x10, 0x7d },
{ 0x11, 0x01 },
{ 0x12, 0x00 },
{ 0x13, 0x06 },
{ 0x14, 0x09 },
{ 0x15, 0x00 },
{ 0x16, 0x05 },
{ 0x17, 0x00 },
{ 0x18, 0x07 },
{ 0x19, 0x00 },
{ 0x1a, 0x00 },
{ 0x1b, 0x00 },
{ 0x1c, 0x02 },
{ 0x1d, 0x00 },
{ 0x1e, 0x00 },
{ 0x1f, 0x0e },
{ 0xa0, 0x01 },
{ 0xa1, 0x00 },
{ 0xa2, 0x00 },
{ 0xa3, 0x01 },
{ 0xa4, 0x00 },
{ 0xa5, 0x00 },
{ 0xa6, 0x01 },
{ 0xa7, 0x00 },
{ 0xa8, 0x00 },
{ 0xa9, 0x01 },
{ 0xaa, 0x00 },
{ 0xab, 0x00 },
{ 0xf0, 0x08 },
{ 0xf1, 0x0a },
{ 0xf2, 0x08 },
{ 0xf3, 0x0a },
{ 0xf4, 0x0a },
{ 0xf5, 0x08 },
{ 0x140, 0x43 },
{ 0x141, 0x42 },
{ 0x142, 0x43 },
{ 0x143, 0x42 },
{ 0x190, 0x00 },
{ 0x191, 0x00 },
{ 0x192, 0x00 },
{ 0x193, 0x88 },
{ 0x194, 0x80 },
{ 0x195, 0x00 },
{ 0x196, 0x00 },
{ 0x197, 0x00 },
{ 0x198, 0x00 },
{ 0x199, 0x00 },
{ 0x19a, 0x00 },
{ 0x19b, 0x00 },
{ 0x19c, 0x00 },
{ 0x19d, 0x00 },
{ 0x19e, 0x00 },
{ 0x19f, 0x00 },
{ 0x1a0, 0x00 },
{ 0x1a1, 0x00 },
{ 0x1a2, 0x00 },
{ 0x1a3, 0x00 },
{ 0x1e0, 0x00 },
{ 0x1e1, 0x01 },
{ 0x230, 0x00 },
{ 0x231, 0x00 },
{ 0x232, 0x00 },
}
};
{
83,
{
{ 0x00, 0x00 },
{ 0x02, 0x00 },
{ 0x03, 0x00 },
{ 0x04, 0x01 }, // readback active
{ 0x05, 0x00 },
{ 0x06, 0x00 },
{ 0x10, 0x7c },
{ 0x11, 0x01 },
{ 0x12, 0x00 },
{ 0x13, 0x00 },
{ 0x14, 0x03 },
{ 0x15, 0x00 },
{ 0x16, 0x04 },
{ 0x17, 0x01 << 2 }, // status -> N div out
{ 0x18, 0x07 },
{ 0x19, 0x00 },
{ 0x1a, 0x00 },
{ 0x1b, 0x00 },
{ 0x1c, 0x00 },
{ 0x1d, 0x80 },
{ 0x1e, 0x00 },
{ 0x1f, 0x00 },
{ 0x20, 0x00 },
{ 0xf0, 0x64 },
{ 0xf1, 0x64 },
{ 0xf2, 0x64 },
{ 0xf3, 0x64 },
{ 0xf4, 0x64 },
{ 0xf5, 0x64 },
{ 0xf6, 0x64 },
{ 0xf7, 0x64 },
{ 0xf8, 0x64 },
{ 0xf9, 0x64 },
{ 0xfa, 0x64 },
{ 0xfb, 0x64 },
{ 0xfc, 0x00 },
{ 0xfd, 0x00 },
{ 0xfe, 0x00 },
{ 0x190, 0x11 },
{ 0x191, 0xc0 },
{ 0x192, 0x00 },
{ 0x193, 0x11 },
{ 0x194, 0xc0 },
{ 0x195, 0x00 },
{ 0x196, 0x11 },
{ 0x197, 0xc0 },
{ 0x198, 0x00 },
{ 0x199, 0x11 },
{ 0x19a, 0xc0 },
{ 0x19b, 0x00 },
{ 0x19c, 0x00 },
{ 0x1e0, 0x00 },
{ 0x1e1, 0x21 },
{ 0x230, 0x00 },
{ 0x231, 0x00 },
{ 0x232, 0x00 },
{ 0xa00, 0x00 },
{ 0xa01, 0x00 },
{ 0xa02, 0x00 },
{ 0xa03, 0x02 },
{ 0xa04, 0x00 },
{ 0xa05, 0x04 },
{ 0xa06, 0x0e },
{ 0xa07, 0x00 },
{ 0xa08, 0x10 },
{ 0xa09, 0x0e },
{ 0xa0a, 0x00 },
{ 0xa0b, 0xf0 },
{ 0xa0c, 0x0b },
{ 0xa0d, 0x01 },
{ 0xa0e, 0x90 },
{ 0xa0f, 0x01 },
{ 0xa10, 0x01 },
{ 0xa11, 0xe0 },
{ 0xa12, 0x01 },
{ 0xa13, 0x02 },
{ 0xa14, 0x30 },
{ 0xa15, 0x80 },
{ 0xa16, 0xff },
{ 0xb00, 0x00 },
{ 0xb01, 0x00 },
{ 0xb02, 0x00 },
{ 0xb03, 0x00 },
}
};
"AD9520 Setup File"
"Rev.","0.0.1"
""
"Addr(Hex)","Value(Bin)","Value(Hex)"
"0000","00000000","00"
"0002","00000000","00"
"0003","00000000","00"
"0004","00000000","00"
"0005","00000000","00"
"0006","00000000","00"
"0010","01111101","7D"
"0011","00000001","01"
"0012","00000000","00"
"0013","00000000","00"
"0014","00000011","03"
"0015","00000000","00"
"0016","00000110","06"
"0017","00000000","00"
"0018","00000110","06"
"0019","00000000","00"
"001A","00000000","00"
"001B","00000000","00"
"001C","01000000","40"
"001D","10000000","80"
"001E","00000000","00"
"001F","00000000","00"
"0020","00000000","00"
"00F0","01100100","64"
"00F1","01100100","64"
"00F2","01100100","64"
"00F3","01100100","64"
"00F4","01100100","64"
"00F5","01100100","64"
"00F6","01100100","64"
"00F7","01100100","64"
"00F8","01100100","64"
"00F9","01100100","64"
"00FA","01100100","64"
"00FB","01100100","64"
"00FC","00000000","00"
"00FD","00000000","00"
"00FE","00000000","00"
"0190","00110011","33"
"0191","00000000","00"
"0192","00000000","00"
"0193","00110011","33"
"0194","00000000","00"
"0195","00000000","00"
"0196","00110011","33"
"0197","00000000","00"
"0198","00000000","00"
"0199","00110011","33"
"019A","00000000","00"
"019B","00000000","00"
"019C","00000000","00"
"01E0","00000000","00"
"01E1","00100001","21"
"0230","00000000","00"
"0231","00000000","00"
"0232","00000000","00"
"0A00","00000000","00"
"0A01","00000000","00"
"0A02","00000000","00"
"0A03","00000010","02"
"0A04","00000000","00"
"0A05","00000100","04"
"0A06","00001110","0E"
"0A07","00000000","00"
"0A08","00010000","10"
"0A09","00001110","0E"
"0A0A","00000000","00"
"0A0B","11110000","F0"
"0A0C","00001011","0B"
"0A0D","00000001","01"
"0A0E","10010000","90"
"0A0F","00000001","01"
"0A10","00000001","01"
"0A11","11100000","E0"
"0A12","00000001","01"
"0A13","00000010","02"
"0A14","00110000","30"
"0A15","10000000","80"
"0A16","11111111","FF"
"0B00","00000000","00"
"0B01","00000000","00"
"0B02","00000000","00"
"0B03","00000000","00"
"","",""
"Other Settings..."
"REF 1:",30.72
"REF 2:",30.72
"VCO:",2949.12
"CLK:",1000
"CPRSet:",5100
"Auto Update:",1
"Load All Regs:",0
""
"CheckSum Values"
"8-Bit Device Checksum (uses R0x000 to R0x232): ","0x6EA"
"8-Bit Data Pattern Checksum (all regs): ","0xB3C"
"16-Bit Device Checksum (uses R0x000 to R0x232): ","0x3638A"
"16-Bit Data Pattern Checksum (all regs): ","0x5CD74"
// this is the default bootstrap config for LTC6950:
// R divider = 1
// N divider = 100
// LV/CM output: bypass divider (forward whatever OCXO produces to the FPGA)
{
23,
{{0x00, 0x00},
{0x01, 0x00},
{0x02, 0x00},
{0x03, 0x08},
{0x04, 0x00},
{0x05, 0x0b}, // CP current = 11.2 mA
{0x06, 0x00},
{0x07, 0x00},
{0x08, 0x01},
{0x09, 0x00},
{0x0a, 0x64}, // N divider = 100 (VCO @ 1GHz, PFD @ 10 MHz)
{0x0b, 0x04}, // disable FILTR for 100 MHz
{0x0c, 0x00},
{0x0d, 0x81},
{0x0e, 0x00},
{0x0f, 0x84}, // 250 MHz
{0x10, 0x00},
{0x11, 0x80},
{0x12, 0x00},
{0x13, 0x80},
{0x14, 0x00},
{0x15, 0x81}, // RDIVOUT = 1 (drive LV/CM with R divider output)
{0x16, 0x00}}
};
python ./ad9510_convert_regs.py ertm_14_pll_main_dot050.stp > ertm_14_pll_main_dot050_config.h
\ No newline at end of file
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* ertm14_dds_sync - driver for DDS Sync Unit (fine pulse generator) */
#include "board.h"
#include "dev/ad9910.h"
#include "hw/wb_dds_sync_unit.h"
#include "dds_sync_unit.h"
#define DS_CSR_FORCE0_OFFSET 8 // fixme
void dds_sync_unit_create( struct dds_sync_unit_device *dev, uint32_t base )
{
int i;
dev->base = (void*) base;
writel( DS_CSR_PLL_RST, dev->base + DS_REG_CSR ); // reset pll
usleep(10);
writel( 0, dev->base + DS_REG_CSR ); // un-reset pll
for(i=0;i<DDS_SYNC_N_CHANNELS;i++)
{
dev->channels[i].delay_tap_size = 78 /* ps */;
dev->channels[i].index = i;
}
}
void dds_sync_unit_setup_channel ( struct dds_sync_unit_device* dev, int ch, int enable, int pps_offset_ps, int polarity, int continuous )
{
dev->channels[ch].flags = (enable ? DDS_SYNC_ENABLED : 0 );
dev->channels[ch].pps_offset_ps = pps_offset_ps;
if(polarity)
dev->channels[ch].flags |= DDS_SYNC_NEGATIVE;
if(continuous)
dev->channels[ch].flags |= DDS_SYNC_CONTINUOUS;
}
void dds_sync_unit_set_external_fine_delay ( struct dds_sync_unit_device* dev, int ch, int tap_size, int (*set_external_delay)( struct dds_sync_unit_channel* ch, int ) )
{
dev->channels[ch].flags |= DDS_SYNC_USE_EXT_FINE_DELAY;
dev->channels[ch].delay_tap_size = tap_size;
dev->channels[ch].set_external_delay = set_external_delay;
}
void dds_sync_force_pulse( struct dds_sync_unit_device* dev, int channel )
{
struct dds_sync_unit_channel* ch = &dev->channels[channel];
int polarity = ch->flags & DDS_SYNC_NEGATIVE;
uint32_t ocr = (1 << DS_OCR0_PPS_OFFS_SHIFT)
| (0x0 << DS_OCR0_MASK_SHIFT)
| (0 << DS_OCR0_FINE_SHIFT)
| (polarity ? DS_OCR0_POL : 0 );
writel( ocr, dev->base + DS_REG_OCR0 + 4 * channel); // configure
uint32_t trig_mask = ( 1 << ( channel + DS_CSR_FORCE0_OFFSET) );
// pp_printf("ForceSync ch %x ocr %x mask %x\n", channel, ocr, trig_mask);
writel( trig_mask, dev->base + DS_REG_CSR ); // configure
}
static uint8_t rotr( uint8_t x, int n )
{
return (x >> n) | (x << (8-n) );
}
void dds_sync_unit_trigger( struct dds_sync_unit_device* dev, uint32_t mask, int force_now )
{
int i;
uint32_t trig_mask = 0;
for(i = 0 ; i < DDS_SYNC_N_CHANNELS; i++ )
{
struct dds_sync_unit_channel* ch = &dev->channels[i];
if( (ch->flags & DDS_SYNC_ENABLED) && ( mask & (1<<i)))
{
uint32_t ocr;
int polarity = ch->flags & DDS_SYNC_NEGATIVE;
int continuous = ch->flags & DDS_SYNC_CONTINUOUS;
uint32_t coarse_par = ch->pps_offset_ps / 16000; // refclk period = 16 ns = 16000 ps
uint32_t coarse_ser = ch->pps_offset_ps / 2000 - coarse_par * 8;
uint32_t fine = (ch->pps_offset_ps % 2000) / ch->delay_tap_size;
uint32_t mask = coarse_ser; // 24/09 VHDL generates mask internally
ocr = (coarse_par << DS_OCR0_PPS_OFFS_SHIFT)
| (mask << DS_OCR0_MASK_SHIFT)
| (fine << DS_OCR0_FINE_SHIFT)
| (polarity ? DS_OCR0_POL : 0 )
| (continuous ? DS_OCR0_CONT : 0 );
//pp_printf("Channel %d OCR %x\n", c->index, ocr );
writel( ocr, dev->base + DS_REG_OCR0 + 4 * i); // configure
if(ch->flags & DDS_SYNC_USE_EXT_FINE_DELAY)
{
ch->set_external_delay( ch, fine );
}
trig_mask |= (1<<i);
}
}
// pp_printf("TrigMask %x\n", trig_mask );
if(force_now)
trig_mask <<= DS_CSR_FORCE0_OFFSET; // fixme: use bitshifts from header file
writel( trig_mask, dev->base + DS_REG_CSR); // arm trigger
}
int dds_sync_unit_poll( struct dds_sync_unit_device* dev, uint32_t mask )
{
uint32_t rv = readl( dev->base + DS_REG_CSR);
int i;
for(i = 0 ; i < DDS_SYNC_N_CHANNELS; i++ )
{
if( (mask & (1<<i)) == 0 )
continue;
struct dds_sync_unit_channel* ch = &dev->channels[i];
uint32_t mask = 1 << ( DS_CSR_READY_SHIFT + i);
if( (ch->flags & DDS_SYNC_ENABLED) && ( (rv & mask) == 0 ) )
return 0;
}
return 1;
}
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ERTM14_DDS_SYNC_H
#define __ERTM14_DDS_SYNC_H
#define DDS_SYNC_ENABLED 0x1
#define DDS_SYNC_NEGATIVE 0x2
#define DDS_SYNC_USE_EXT_FINE_DELAY 0x4
#define DDS_SYNC_CONTINUOUS 0x8
#define DDS_SYNC_N_CHANNELS 6
// sync unit channels
// SYNC_IN(+/-) of AD9910
#define ERTM14_DDS_SYNC_LO 0
#define ERTM14_DDS_SYNC_REF 1 // fixme: inverted cannel order in HDL
// SYNC_N inputs of the AD9520s (backplane clock distribution)
#define ERTM14_PLL_SYNC_CLKA 2
#define ERTM14_PLL_SYNC_CLKB 3
// I/O_UPDATE(+/-) of AD9910
#define ERTM14_DDS_IOUPDATE_LO 4
#define ERTM14_DDS_IOUPDATE_REF 5
struct dds_sync_unit_channel {
uint32_t flags;
int pps_offset_ps;
int index;
int delay_tap_size;
int (*set_external_delay)( struct dds_sync_unit_channel* ch, int n_taps );
};
struct dds_sync_unit_device {
void* base;
struct dds_sync_unit_channel channels[DDS_SYNC_N_CHANNELS];
};
void dds_sync_unit_create( struct dds_sync_unit_device *dev, uint32_t base );
void dds_sync_unit_setup_channel ( struct dds_sync_unit_device* dev, int ch, int enable, int pps_offset_ps, int polarity, int continuous );
void dds_sync_unit_set_external_fine_delay ( struct dds_sync_unit_device* dev, int ch, int tap_size, int (*set_external_delay)( struct dds_sync_unit_channel* ch, int ) );
void dds_sync_unit_trigger( struct dds_sync_unit_device* dev, uint32_t mask, int force_now );
void dds_sync_force_pulse( struct dds_sync_unit_device* dev, int ch );
int dds_sync_unit_poll( struct dds_sync_unit_device* dev, uint32_t mask );
#endif
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <stdio.h>
#include <stdint.h>
#include <math.h>
#include "board.h"
#include "dev/gpio.h"
#include "dev/74x595.h"
#include "dev/ad7888.h"
#include "ertm15_rf_distr.h"
static const struct gpio_pin pin_lo_ctrl_ser = { &board.gpio_aux, 39 };
static const struct gpio_pin pin_lo_ctrl_updtclk = { &board.gpio_aux, 40 };
static const struct gpio_pin pin_lo_ctrl_shftclk = { &board.gpio_aux, 41 };
static const struct gpio_pin pin_ref_ctrl_ser = { &board.gpio_aux, 42 };
static const struct gpio_pin pin_ref_ctrl_updtclk = { &board.gpio_aux, 43 };
static const struct gpio_pin pin_ref_ctrl_shftclk = { &board.gpio_aux, 44 };
static struct gpio_device gpio_rfsw_ref;
static struct gpio_device gpio_rfsw_lo;
// mapping between x595 shift reg (IC26..28 on eRTM15 and the RF switch control pins)
static const struct pin_mapping
{
uint8_t path; // RF path (REF/LO)
uint8_t channel; // MTCA.4 channel
uint8_t ctrl1, ctrl2; // RF switch pin indices (CTRL1/CTRL2)
} rf_switch_sreg_pin_mapping[] = {
// REF outputs
{ERTM15_RF_REF, 4, 8 + 5, 8 + 4},
{ERTM15_RF_REF, 5, 8 + 6, 8 + 7},
{ERTM15_RF_REF, 6, 8 + 1, 8 + 0},
{ERTM15_RF_REF, 7, 8 + 3, 8 + 2},
{ERTM15_RF_REF, 8, 4, 5},
{ERTM15_RF_REF, 9, 6, 7},
{ERTM15_RF_REF, 10, 16 + 7, 16 + 6},
{ERTM15_RF_REF, 11, 2, 3},
{ERTM15_RF_REF, 12, 0, 1},
// LO outputs
{ERTM15_RF_LO, 4, 16 + 7, 16 + 6}, // ic28 7, 6
{ERTM15_RF_LO, 5, 0 + 6, 0 + 7}, // ic26 6, 7
{ERTM15_RF_LO, 6, 0 + 4, 0 + 5}, // ic26 4, 5
{ERTM15_RF_LO, 7, 0 + 0, 0 + 1}, // ic26 15, 1
{ERTM15_RF_LO, 8, 0 + 2, 0 + 3}, // ic26 2, 3
{ERTM15_RF_LO, 9, 8 + 6, 8 + 7}, // ic27 6, 7
{ERTM15_RF_LO, 10, 8 + 5, 8 + 4}, // ic27 5, 4
{ERTM15_RF_LO, 11, 8 + 1, 8 + 0}, // ic27 1, 15
{ERTM15_RF_LO, 12, 8 + 3, 8 + 2}, // ic27 3, 2
{ERTM15_RF_REF, 0, 0, 0}};
static const struct pin_mapping* find_pins_for_channel ( int path, int channel )
{
int i;
for(i=0; rf_switch_sreg_pin_mapping[i].channel !=0; i++ )
{
if( rf_switch_sreg_pin_mapping[i].channel == channel && rf_switch_sreg_pin_mapping[i].path == path )
{
return &rf_switch_sreg_pin_mapping[i];
}
}
return NULL;
}
static int rf_switch_set( int path, int channel, int state)
{
struct gpio_device *gpio = ( path == ERTM15_RF_REF ? &gpio_rfsw_ref : &gpio_rfsw_lo);
const struct pin_mapping *pins = find_pins_for_channel( path, channel );
struct gpio_pin ctrl1, ctrl2;
ctrl1.device = gpio;
ctrl1.pin = pins->ctrl1;
ctrl2.device = gpio;
ctrl2.pin = pins->ctrl2;
if(!pins)
return -1;
// HSWA2-30DR+ I/O CTRL pins function:
// CTRL1 = 0, CTRL2 = 0: OFF
// CTRL1 = 0, CTRL2 = 1: MONITOR
// CTRL1 = 1, CTRL2 = 0: ON
switch(state)
{
case ERTM15_RF_OUT_ON:
gen_gpio_out( &ctrl1, 1 );
gen_gpio_out( &ctrl2, 0 );
break;
case ERTM15_RF_OUT_MONITOR:
gen_gpio_out( &ctrl1, 0 );
gen_gpio_out( &ctrl2, 1 );
break;
case ERTM15_RF_OUT_OFF:
gen_gpio_out( &ctrl1, 0 );
gen_gpio_out( &ctrl2, 0 );
break;
}
return 0;
}
void ertm15_rf_distr_init( struct ertm15_rf_distribution_device *dev, struct ad7888_device *pwr_mon_adc )
{
x595_gpio_create ( &gpio_rfsw_ref, 3, &pin_ref_ctrl_updtclk, &pin_ref_ctrl_shftclk, NULL, &pin_ref_ctrl_ser );
x595_gpio_create ( &gpio_rfsw_lo, 3, &pin_lo_ctrl_updtclk, &pin_lo_ctrl_shftclk, NULL, &pin_lo_ctrl_ser );
//x595_test( &gpio_rfsw_ref );
dev->pwr_ref_valid = 0;
dev->pwr_lo_valid = 0;
dev->ref_enabled = 0;
dev->lo_enabled = 0;
dev->pwr_ref_valid = 0;
dev->pwr_mon_adc = pwr_mon_adc;
// disable all RF outputs to the backplane
ertm15_update_rf_switches( dev );
}
static int convert_power( int adc_value )
{
//pp_printf("ADCV %d\n", adc_value );
float adc_voltage = (float) adc_value / 4096.0 * 2.5;
float rf_power = 10.0 * log( adc_voltage / 2.0 ) / log( 10.0 ) + 15.0; // 2V = 0 dBm, compensate for 15 dB attenuator
return (int) (rf_power * 100.0);
}
#define ADC_CH_REF_DDS_PA 2
#define ADC_CH_LO_DDS_PA 0
#define ADC_CH_REF_DDS_DISTR 3
#define ADC_CH_LO_DDS_DISTR 1
int ertm15_rf_distr_measure_power ( struct ertm15_rf_distribution_device *dev )
{
ad7888_start_conversion( dev->pwr_mon_adc, 0x0f );
while( dev->pwr_mon_adc->channel_valid != 0x0f )
{
ad7888_poll( dev->pwr_mon_adc );
usleep(1000);
}
dev->pwr_ref_in = convert_power( dev->pwr_mon_adc->channel[ADC_CH_REF_DDS_PA] );
dev->pwr_lo_in = convert_power( dev->pwr_mon_adc->channel[ADC_CH_LO_DDS_PA] );
int i;
for( i = 4; i <= 12; i ++ )
{
dev->pwr_ref_valid &= ~(1<<i);
if( ! (dev->ref_enabled & (1<<i) ) )
{
rf_switch_set( ERTM15_RF_REF, i, ERTM15_RF_OUT_MONITOR );
usleep(10000);
int raw_pwr = ad7888_meas_channel( dev->pwr_mon_adc, ADC_CH_REF_DDS_DISTR );
dev->pwr_ref_ch[ i ] = convert_power( raw_pwr );
pp_printf("Ch REF %d: pwr %d v %d\n", i, dev->pwr_ref_ch[i], dev->pwr_mon_adc->channel_valid );
dev->pwr_ref_valid |= (1<<i);
rf_switch_set( ERTM15_RF_REF, i, ERTM15_RF_OUT_OFF );
}
}
return 0;
}
void ertm15_rf_distr_output_enable( struct ertm15_rf_distribution_device *dev, int path, int channel, int enabled )
{
uint16_t* mask = (path == ERTM15_RF_LO ? &dev->lo_enabled : &dev->ref_enabled );
if( enabled )
*mask |= ( 1 << channel );
else
*mask &= ~( 1 << channel );
}
void ertm15_update_rf_switches( struct ertm15_rf_distribution_device *dev )
{
int i;
for( i = 0; rf_switch_sreg_pin_mapping[i].channel != 0; i++ )
{
const struct pin_mapping* p = &rf_switch_sreg_pin_mapping[i];
int enabled = ( p->path == ERTM15_RF_LO ? dev->lo_enabled : dev->ref_enabled ) & (1 << p->channel );
pp_printf("rf_distr: switch %s ch %d -> %s\n", p->path == ERTM15_RF_LO ? "LO" : "REF", p->channel, enabled ? "ON" : "OFF" );
rf_switch_set( p->path, p->channel, enabled ? ERTM15_RF_OUT_ON : ERTM15_RF_OUT_OFF );
}
}
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2019 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation, either version 3 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ERTM15_RF_DISTR_H
#define __ERTM15_RF_DISTR_H
#include <stdint.h>
#define ERTM15_RF_OUT_ON 0
#define ERTM15_RF_OUT_MONITOR 1
#define ERTM15_RF_OUT_OFF 2
#define ERTM15_RF_LO 0
#define ERTM15_RF_REF 1
struct ad7888_device;
struct ertm15_rf_distribution_device {
uint16_t pwr_lo_valid;
uint16_t lo_enabled;
uint16_t pwr_ref_valid;
uint16_t ref_enabled;
int pwr_lo_ch [ 16 ];
int pwr_ref_ch [ 16 ];
int pwr_lo_in;
int pwr_ref_in;
struct ad7888_device *pwr_mon_adc;
};
void ertm15_rf_distr_init( struct ertm15_rf_distribution_device *dev, struct ad7888_device *pwr_mon_adc );
int ertm15_rf_distr_measure_power ( struct ertm15_rf_distribution_device *dev );
void ertm15_rf_distr_output_enable( struct ertm15_rf_distribution_device *dev, int path, int channel, int enabled );
void ertm15_update_rf_switches( struct ertm15_rf_distribution_device *dev );
#endif
/*
Register definitions for slave core: 10 MHz Output Aligner Unit
* File : 10mhz_align_unit.h
* Author : auto-generated by wbgen2 from 10mhz_align_unit_wb.wb
* Created : Sun Sep 8 01:41:43 2019
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE 10mhz_align_unit_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_10MHZ_ALIGN_UNIT_WB_WB
#define __WBGEN2_REGDEFS_10MHZ_ALIGN_UNIT_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control/Status Register */
/* definitions for field: Measurement trigger in reg: Control/Status Register */
#define TAU_CSR_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Measurement complete in reg: Control/Status Register */
#define TAU_CSR_DONE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Measured offset in reg: Control/Status Register */
#define TAU_CSR_OFFSET_MASK WBGEN2_GEN_MASK(2, 12)
#define TAU_CSR_OFFSET_SHIFT 2
#define TAU_CSR_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 2, 12)
#define TAU_CSR_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 2, 12)
/* definitions for register: IDELAY Control */
/* definitions for field: Load in reg: IDELAY Control */
#define TAU_IDELAY_CR_LOAD WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Delay Taps in reg: IDELAY Control */
#define TAU_IDELAY_CR_TAPS_MASK WBGEN2_GEN_MASK(1, 5)
#define TAU_IDELAY_CR_TAPS_SHIFT 1
#define TAU_IDELAY_CR_TAPS_W(value) WBGEN2_GEN_WRITE(value, 1, 5)
#define TAU_IDELAY_CR_TAPS_R(reg) WBGEN2_GEN_READ(reg, 1, 5)
/* definitions for register: Dummy */
/* definitions for field: Load in reg: Dummy */
#define TAU_DUMMY_LOAD WBGEN2_GEN_MASK(0, 1)
/* [0x0]: REG Control/Status Register */
#define TAU_REG_CSR 0x00000000
/* [0x4]: REG IDELAY Control */
#define TAU_REG_IDELAY_CR 0x00000004
/* [0x8]: REG Dummy */
#define TAU_REG_DUMMY 0x00000008
#endif
This diff is collapsed.
This diff is collapsed.
......@@ -23,6 +23,8 @@
# include "boards/wr-switch/board.h"
#elif defined(CONFIG_TARGET_AFCZ)
# include "boards/afcz/board.h"
#elif defined(CONFIG_TARGET_ERTM14)
# include "boards/ertm14/board.h"
#endif
......
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