• Grzegorz Daniluk's avatar
    spll: lock offset frequency below the ref frequency · 0376b6f1
    Grzegorz Daniluk authored
    Reason: h_y was close to the DAC range, on some boards we were unable to lock
    HPLL.
    In addition to HPLL modifications, also the phase shifting had to be changed.
    When offset clock has lower frequency than the ref clock, shifting ref
    clock produces sampled clock which is shifted in another direction.
    0376b6f1
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