Schematics review 26/10/2016
File used for the review: https://www.ohwr.org/project/wrs-low-jitter/uploads/7eb96aa55ee2b102a6b9b5437f5f4a41/Daughterboard_V2.pdf
Present
Van der Bij Erik (BE/CO), Boucquey Nicolas (BE/CO), Calvo Giraldo Eva (BE/CO), Daniluk Grzegorz (BE/CO), Van der Bij Erik (BE/CO), Lampridis Dimitrios (BE/CO), Gousiou Evangelia (BE/CO), Lipinski Maciej (BE/CO)
Detailed comments on schematics
General comments
- Disable the dot marking on the labels of components
(Tools
Schematics>Marking, disable it) - Use a yellow frame for the notes
Top Level sheet
- Refactor the block diagram in order to be read from left to right, top to bottom
- Power block diagram floating, not connected to the power connector
- Move all the connectors to the top level sheet (including debug connectors)
Power
- The voltage divider used in the feedback loop of IC1 it's not clear
Oscillator
- Refactor the connections, must be readable from left to right
- Missing a _N in the net DAC_REF_SYNC of the DAC (IC5)
- Directly connect the output of the VCTCXO to IC7
PLL
- Differential marking are not displayed on the IC8 outputs from OUT0 to OUT5, contact CERN Library service
- Refactor the IC8 Loop filter, it's not clear. Connect it directly to IC8, do not leave it floating
FPGA connector
- Make the OSC_FREQUENCY_ID lines user selectable with jumpers rather than using SMD resistors
- Place a silkscreen on the PCB explaining the meaning of the jumpers