board      = "svec"
sim_tool   = "modelsim"
sim_top    = "main"
action     = "simulation"
target     = "xilinx"
syn_device = "xc6slx150t"
vcom_opt   = "-93 -mixedsvvh"

fetchto="../../../dependencies"

sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"

include_dirs = [
    "../include",
    fetchto + "/general-cores/sim/",
    fetchto + "/mock-turtle/hdl/testbench/include/",
]

files = [
    "main.sv",
    "dut_env.sv",
    "synthesis_descriptor.vhd",
]

modules = {
    "local" : [
        "../../top/wrtd_ref_svec_tdc_fd",
    ],
}
