.. _svec_ref_tdc_fd:

SVEC-based TDC+FD
=================

+----------------------------------------+------------+------------+
| **Parameter**                          |        **Value**        |
+========================================+============+============+
| # of :ref:`Applications <application>` |            2            |
+----------------------------------------+------------+------------+
|                                        | **App #1** | **App #2** |
+----------------------------------------+------------+------------+
|  Name                                  |  wrtd-tdc  |   wrtd-fd  |
+----------------------------------------+------------+------------+
|  Local input Channels                  |      5     |      0     |
+----------------------------------------+------------+------------+
|  Local output Channels                 |      0     |      4     |
+----------------------------------------+------------+------------+
|  Maximum :ref:`Rules <rule>`           |     16     |     16     |
+----------------------------------------+------------+------------+
|  Maximum :ref:`Alarms <alarm>`         |      0     |      1     |
+----------------------------------------+------------+------------+
|  Average input to Message latency      | 20μs (TBC) |     N.A.   |
+----------------------------------------+------------+------------+
|  Average Message to output latency     |     N.A.   | 40μs (TBC) |
+----------------------------------------+------------+------------+
|  Can receive Messages over WR          |      NO    |     YES    |
+----------------------------------------+------------+------------+
|  Can send Messages over WR             |     YES    |      NO    |
+----------------------------------------+------------+------------+

This is a WRTD :ref:`node` based on the `Simple VME FMC Carrier (SVEC)
<https://www.ohwr.org/project/svec/wikis/home>`_, the `FMC Time to Digital Converter (FMC-TDC)
<https://www.ohwr.org/project/fmc-tdc-1ns-5cha-hw/wikis/home>`_ and the `FMC Fine Delay generator
(FMC-FD) <https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/home>`_.

.. important:: The FMC-TDC should always be attached to "FMC Slot 1" of the SVEC, and the FMC-FD
               should always be attached to "FMC Slot 2". It is not necessary though to have both
               the FMCs attached, the :ref:`Node` will work if only one of the two (TDC or FD) is
               present, as long as it is connected to the correct FMC slot.

The basic principle of this :ref:`node` is simple: It takes in external pulses on its FMC-TDC
inputs, timestamps them using WR time and converts them to WRTD :ref:`Messages <message>`, to be
sent over the WR network. Conversely, the :ref:`node` also receives WRTD :ref:`Messages <message>`
which are then used to generate pulses at a predefined moment on one of the FMC-FD outputs. As such,
it can be seen as a "pulse-to-message" and "message-to-pulse" converter with apllications in the
field of pulse distribution, trigger syncrhonisation, etc.

.. figure:: graphics/wrtd_ref_design_svec_list_simple.png
   :name: fig-ref_svec_list
   :width: 400pt
   :align: center
   :alt: alternate text
   :figclass: align-center

   SVEC-based TDC+FD reference WRTD Node

The architecture of the :ref:`node` can be seen in :numref:`fig-ref_svec_list`. The user
communicates with the :ref:`node` using one of the methods mentioned in :numref:`usage`. Internally,
the :ref:`node` is running two :ref:`Applications <application>`, each on a dedicated CPU. One is
responsible for the FMC-TDC peripheral, while the other handles the FMC-FD.

The five :ref:`Local Input Channels <local_channel>` are mapped to the five inputs of the
FMC-TDC. Thus, :ref:`event_id` ``LC-I1`` corresponds to the first FMC-TDC channel, ``LC-I2`` to the
second one, and so on, up to ``LC-I5``.

The four :ref:`Local Output Channels <local_channel>` are mapped to the four outputs of the
FMC-FD. :ref:`event_id` ``LC-O1`` corresponds to the first FMC-FD output, and so on, up to
``LC-O4``.

.. hint:: It is possible for the User Application in :numref:`fig-ref_svec_list` to access directly
          the FMC-TDC and FMC-FD cores by means of their respective libraries (not shown in
          :numref:`fig-ref_svec_list`), in order to fine-tune them and/or change their default
          behaviour. However this should be done with extreme care, as it could lead to a race
          condition between the User Application and the WRTD Applications running inside the FPGA.
