Merge branch 'dlamprid-dev' into wrtd-ng

099de7b2 · Dimitris Lampridis · 57fb00ad · f51f4595 · 099de7b2 · 57fb00ad
Commit 099de7b2 authored Feb 14, 2019 by Dimitris Lampridis
125 changed files
--- a/.gitmodules
+++ b/.gitmodules
 [submodule "dependencies/mock-turtle"]
 	path = dependencies/mock-turtle
-	url = git://ohwr.org/hdl-core-lib/mock-turtle.git
+	url = https://ohwr.org/project/mock-turtle.git
 [submodule "dependencies/fine-delay"]
 	path = dependencies/fmc-delay-1ns-8cha
-	url = git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git
+	url = https://ohwr.org/project/fmc-delay-1ns-8cha.git
 [submodule "dependencies/fmc-tdc"]
 	path = dependencies/fmc-tdc-1ns-5cha-gw
-	url = git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git
+	url = https://ohwr.org/project/fmc-tdc-1ns-5cha-gw.git
 [submodule "dependencies/vme64x-core"]
 	path = dependencies/vme64x-core
-	url = git://ohwr.org/hdl-core-lib/vme64x-core.git
+	url = https://ohwr.org/project/vme64x-core.git
 [submodule "dependencies/general-cores"]
 	path = dependencies/general-cores
-	url = git://ohwr.org/hdl-core-lib/general-cores.git
+	url = https://ohwr.org/project/general-cores.git
 [submodule "dependencies/wr-cores"]
 	path = dependencies/wr-cores
-	url = git://ohwr.org/hdl-core-lib/wr-cores.git
+	url = https://ohwr.org/project/wr-cores.git
 [submodule "dependencies/urv-core"]
 	path = dependencies/urv-core
-	url = git://ohwr.org/hdl-core-lib/urv-core.git
+	url = https://ohwr.org/project/urv-core.git
 [submodule "dependencies/fmc-adc-100m14b4cha-gw"]
 	path = dependencies/fmc-adc-100m14b4cha-gw
-	url = git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git
+	url = https://ohwr.org/project/fmc-adc-100m14b4cha-gw.git
 [submodule "dependencies/ddr3-sp6-core"]
 	path = dependencies/ddr3-sp6-core
-	url = git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
+	url = https://ohwr.org/project/ddr3-sp6-core.git
 [submodule "dependencies/gn4124-core"]
 	path = dependencies/gn4124-core
-	url = git://ohwr.org/hdl-core-lib/gn4124-core.git
+	url = https://ohwr.org/project/gn4124-core.git
--- a/builder/hdl/syn/svec_adc/svec_adc.ucf
+++ b/builder/hdl/syn/svec_adc/svec_adc.ucf
--- a/builder/hdl/syn/svec_fd_tdc/Manifest.py
+++ b/builder/hdl/syn/svec_fd_tdc/Manifest.py
-# HDLMake 'develop' branch required.
-#
-# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
-# branch of hdlmake, commit db4e1ab.
-
-board  = "svec"
-target = "xilinx"
-action = "synthesis"
-
-syn_device  = "xc6slx150t"
-syn_grade   = "-3"
-syn_package = "fgg900"
-syn_top     = "svec_fd_tdc_top"
-syn_project = "svec_fd_tdc.xise"
-syn_tool    = "ise"
-
-fetchto = "../../../../dependencies"
-
-syn_post_project_cmd = (
-    "$(TCL_INTERPRETER) " + \
-    fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
-    syn_tool + " $(PROJECT_FILE);" \
-    "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
-)
-
-files = [
-    "svec_fd_tdc.ucf",
-]
-
-modules = {
-    "local" : [
-        "../../top/svec_fd_tdc",
-    ],
-}
--- a/builder/hdl/syn/svec_fd_tdc/svec_fd_tdc.ucf
+++ b/builder/hdl/syn/svec_fd_tdc/svec_fd_tdc.ucf
--- a/builder/hdl/syn/svec_tdc_fd/Manifest.py
+++ b/builder/hdl/syn/svec_tdc_fd/Manifest.py
-# HDLMake 'develop' branch required.
-#
-# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
-# branch of hdlmake, commit db4e1ab.
-
-board  = "svec"
-target = "xilinx"
-action = "synthesis"
-
-syn_device  = "xc6slx150t"
-syn_grade   = "-3"
-syn_package = "fgg900"
-syn_top     = "svec_tdc_fd_top"
-syn_project = "svec_tdc_fd.xise"
-syn_tool    = "ise"
-
-fetchto = "../../../../dependencies"
-
-syn_post_project_cmd = (
-    "$(TCL_INTERPRETER) " + \
-    fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
-    syn_tool + " $(PROJECT_FILE);" \
-    "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
-)
-
-files = [
-    "svec_tdc_fd.ucf",
-]
-
-modules = {
-    "local" : [
-        "../../top/svec_tdc_fd",
-    ],
-}
--- a/builder/hdl/syn/svec_tdc_fd/svec_tdc_fd.ucf
+++ b/builder/hdl/syn/svec_tdc_fd/svec_tdc_fd.ucf
--- a/builder/hdl/top/svec_adc/Manifest.py
+++ b/builder/hdl/top/svec_adc/Manifest.py
-files = [
-    "svec_adc_top.vhd",
-]
-
-fetchto = "../../../../dependencies"
-
-modules = {
-    "git" : [
-        "git://ohwr.org/hdl-core-lib/general-cores.git",
-        "git://ohwr.org/hdl-core-lib/wr-cores.git",
-        "git://ohwr.org/hdl-core-lib/vme64x-core.git",
-        "git://ohwr.org/hdl-core-lib/urv-core.git",
-        "git://ohwr.org/hdl-core-lib/mock-turtle.git",
-        "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
-        "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git",
-
-    ],
-}
--- a/builder/hdl/top/svec_adc/svec_adc_top.vhd
+++ b/builder/hdl/top/svec_adc/svec_adc_top.vhd
--- a/builder/hdl/top/svec_fd_tdc/Manifest.py
+++ b/builder/hdl/top/svec_fd_tdc/Manifest.py
-files = [
-    "svec_fd_tdc_top.vhd",
-]
-
-fetchto = "../../../../dependencies"
-
-modules = {
-    "git" : [
-        "git://ohwr.org/hdl-core-lib/general-cores.git",
-        "git://ohwr.org/hdl-core-lib/wr-cores.git",
-        "git://ohwr.org/hdl-core-lib/vme64x-core.git",
-        "git://ohwr.org/hdl-core-lib/urv-core.git",
-        "git://ohwr.org/hdl-core-lib/mock-turtle.git",
-        "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git",
-        "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git",
-
-    ],
-}
--- a/builder/hdl/top/svec_fd_tdc/svec_fd_tdc_top.vhd
+++ b/builder/hdl/top/svec_fd_tdc/svec_fd_tdc_top.vhd
--- a/builder/hdl/top/svec_tdc_fd/Manifest.py
+++ b/builder/hdl/top/svec_tdc_fd/Manifest.py
-files = [
-    "svec_tdc_fd_top.vhd",
-]
-
-fetchto = "../../../../dependencies"
-
-modules = {
-    "git" : [
-        "git://ohwr.org/hdl-core-lib/general-cores.git",
-        "git://ohwr.org/hdl-core-lib/wr-cores.git",
-        "git://ohwr.org/hdl-core-lib/vme64x-core.git",
-        "git://ohwr.org/hdl-core-lib/urv-core.git",
-        "git://ohwr.org/hdl-core-lib/mock-turtle.git",
-        "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git",
-        "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git",
-
-    ],
-}
--- a/builder/hdl/top/svec_tdc_fd/svec_tdc_fd_top.vhd
+++ b/builder/hdl/top/svec_tdc_fd/svec_tdc_fd_top.vhd
--- a/ddr3-sp6-core @ bb5b8f75
+++ b/ddr3-sp6-core @ bb5b8f75
-Subproject commit 33b31655be05192c6a0fbb4f3c2d96cf55b3abb6
+Subproject commit bb5b8f75e6f85335b43fef320375404686a74008
--- a/fmc-adc-100m14b4cha-gw @ a60eac03
+++ b/fmc-adc-100m14b4cha-gw @ a60eac03
-Subproject commit 0bf73130484cd9a0f550b68a9cf4ac3996fb526d
+Subproject commit a60eac03a83cf136a5d3effac04346df874a24b0
--- a/general-cores @ caad0595
+++ b/general-cores @ caad0595
-Subproject commit 556e4c16302532ac5cb60150c18add695ea1b337
+Subproject commit caad0595a00d6f69aa59993a790c1aa3c8fd691f
--- a/gn4124-core @ c9d96ee0
+++ b/gn4124-core @ c9d96ee0
-Subproject commit 10cd74b06a094c5b6c1a566676785e1814001404
+Subproject commit c9d96ee08abce9440ec79e5d2c11359876ddb486
--- a/mock-turtle @ 6beecf5a
+++ b/mock-turtle @ 6beecf5a
-Subproject commit e3833c69188bd276af3697e534f6fe455a24cd16
+Subproject commit 6beecf5aa562e81a1170af4edbfb59b49245bfb3
--- a/urv-core @ 5c7e906c
+++ b/urv-core @ 5c7e906c
-Subproject commit 70e9e78f740aa7f4d8168ccaa003bf3924824284
+Subproject commit 5c7e906ceb6b15f53830061c9087cce0befef13a
--- a/wr-cores @ 4f1fafd7
+++ b/wr-cores @ 4f1fafd7
-Subproject commit 0d636aa520d0b547dbb1e8bd6f09d85f21203347
+Subproject commit 4f1fafd72b08dee6ea9ef13715e6e9981e5d5021
--- a/builder/hdl/syn/spec_adc/.gitignore
+++ b/builder/hdl/syn/spec_adc/.gitignore
--- a/builder/hdl/syn/spec_adc/Manifest.py
+++ b/builder/hdl/syn/spec_adc/Manifest.py
@@ -7,14 +7,14 @@ board  = "spec"
 target = "xilinx"
 action = "synthesis"

-syn_device  = "xc6slx100t"
+syn_device  = "xc6slx150t"
 syn_grade   = "-3"
 syn_package = "fgg484"
-syn_top     = "spec_adc_top"
-syn_project = "spec_adc.xise"
+syn_top     = "wrtd_ref_spec150t_adc"
+syn_project = "wrtd_ref_spec150t_adc.xise"
 syn_tool    = "ise"

-fetchto = "../../../../dependencies"
+fetchto = "../../../dependencies"

 ctrls = ["bank3_64b_32b"]

@@ -26,11 +26,11 @@ syn_post_project_cmd = (
 )

 files = [
-    "spec_adc.ucf",
+    "wrtd_ref_spec150t_adc.ucf",
 ]

 modules = {
    "local" : [
-        "../../top/spec_adc",
+        "../../top/wrtd_ref_spec150t_adc",
    ],
 }
--- a/hdl/syn/svec/list_tdc_fd/syn_extra_steps.tcl
+++ b/hdl/syn/svec/list_tdc_fd/syn_extra_steps.tcl
@@ -14,13 +14,19 @@ xilinx::project open $project_file
 # Not respected by ISE when passed through hdlmake:
 # 1. Pack I/O Registers/Latches into IOBs
 # 2. Register Duplication Map
+
 xilinx::project set "Enable Multi-Threading" "2" -process "Map"
 xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
 xilinx::project set "Pack I/O Registers into IOBs" "Yes"
 xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
 xilinx::project set "Register Balancing" "Yes"
 xilinx::project set "Register Duplication Map" "On"

+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
 xilinx::project save

 xilinx::project close
--- a/builder/hdl/syn/spec_adc/spec_adc.ucf
+++ b/builder/hdl/syn/spec_adc/spec_adc.ucf
@@ -214,6 +214,8 @@ NET "fmc0_sda_b"         IOSTANDARD = "LVCMOS25";
 INST "cmp_gn4124_core/cmp_wrapped_gn4124/l2p_rdy_t"   IOB = FALSE;
 INST "cmp_gn4124_core/cmp_wrapped_gn4124/l_wr_rdy_t*" IOB = FALSE;

+NET "fmc?_adc_gpio*" IOB = FALSE;
+
 #===============================================================================
 # Timing constraints and exceptions
 #===============================================================================

--- a/hdl/syn/svec/list_tdc_fd/.gitignore
+++ b/hdl/syn/svec/list_tdc_fd/.gitignore
--- a/hdl/syn/svec/list_tdc_fd/Manifest.py
+++ b/hdl/syn/svec/list_tdc_fd/Manifest.py
@@ -10,11 +10,11 @@ action = "synthesis"
 syn_device  = "xc6slx150t"
 syn_grade   = "-3"
 syn_package = "fgg900"
-syn_top     = "svec_list_top"
-syn_project = "svec_list_tdc_fd.xise"
+syn_top     = "wrtd_ref_svec_tdc_fd"
+syn_project = "wrtd_ref_svec_tdc_fd.xise"
 syn_tool    = "ise"

-fetchto = "../../../../dependencies"
+fetchto = "../../../dependencies"

 syn_post_project_cmd = (
    "$(TCL_INTERPRETER) " + \
@@ -24,11 +24,11 @@ syn_post_project_cmd = (
 )

 files = [
-    "svec_list_top.ucf",
+    "wrtd_ref_svec_tdc_fd.ucf",
 ]

 modules = {
    "local" : [
-        "../../../top/svec/list_tdc_fd",
+        "../../top/wrtd_ref_svec_tdc_fd",
    ],
 }
--- a/builder/hdl/syn/spec_adc/syn_extra_steps.tcl
+++ b/builder/hdl/syn/spec_adc/syn_extra_steps.tcl
--- a/hdl/syn/svec/list_tdc_fd/svec_list_top.ucf
+++ b/hdl/syn/svec/list_tdc_fd/svec_list_top.ucf
--- a/hdl/testbench/Makefile
+++ b/hdl/testbench/Makefile
@@ -3,7 +3,7 @@
 #
 # Author: Adam Wujek, CERN 2017

-TB_DIRS=list
+TB_DIRS = wrtd_ref_svec_tdc_fd wrtd_ref_spec150t_adc

 test_results_xml=test_results.xml
 .PHONY: $(TB_DIRS)
@@ -11,7 +11,8 @@ test_results_xml=test_results.xml
 all: $(TB_DIRS) summary summary_total summary_xml

 FW_BRAM = ../../software/firmware/fd/wrtd-rt-fd.bram \
-  ../../software/firmware/tdc/wrtd-rt-tdc.bram \
+	  ../../software/firmware/tdc/wrtd-rt-tdc.bram \
+	  ../../software/firmware/adc/wrtd-rt-adc.bram

 wrtd-system: $(FW_BRAM)


--- a/hdl/testbench/include/wrtd_alarm.svh
+++ b/hdl/testbench/include/wrtd_alarm.svh
+//------------------------------------------------------------------------------
+// CERN BE-CO-HT
+// White Rabbit Trigger Distribution (WRTD)
+// https://ohwr.org/projects/wrtd
+//------------------------------------------------------------------------------
+//
+// unit name:   WrtdAlarm, WrtdAlarmCollection
+//
+// description: A SystemVerilog Class for a WRTD "alarm" repeated capability
+//
+//------------------------------------------------------------------------------
+// Copyright CERN 2019
+//------------------------------------------------------------------------------
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 2.0 (the "License"); you may not use this file except
+// in compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-2.0.
+// Unless required by applicable law or agreed to in writing, software,
+// hardware and materials distributed under this License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+// or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//------------------------------------------------------------------------------
+
+`ifndef __WRTD_ALARM_INCLUDED
+ `define __WRTD_ALARM_INCLUDED
+
+ `include "wrtd_rep_cap.svh"
+
+class WrtdAlarm extends WrtdRepCap;
+
+   function new ( int core, int index, string name = "" );
+      super.new ( core, index, name );
+      clear();
+   endfunction // new
+
+   function void clear ( );
+      super.clear();
+   endfunction // clear
+
+   function repcap_data data_pack ( );
+   endfunction // data_pack
+
+   function void data_unpack ( repcap_data data );
+   endfunction // data_unpack
+
+endclass //WrtdAlarm
+
+class WrtdAlarmCollection extends WrtdRepCapCollection;
+   protected WrtdAlarm collection[];
+
+   function new ( int size, string name );
+      super.new ( size, name );
+   endfunction // new
+
+endclass // WrtdAlarmCollection
+
+`endif //  `ifndef __WRTD_ALARM_INCLUDED
--- a/hdl/testbench/include/wrtd_definitions.svh
+++ b/hdl/testbench/include/wrtd_definitions.svh
+//------------------------------------------------------------------------------
+// CERN BE-CO-HT
+// White Rabbit Trigger Distribution (WRTD)
+// https://ohwr.org/projects/wrtd
+//------------------------------------------------------------------------------
+//
+// unit name:   WrtdTstamp
+//
+// description: A collection of definitions and types used by the WrtdDev class.
+//
+// These are mostly copy-pasted from the WRTD library.
+//
+//------------------------------------------------------------------------------
+// Copyright CERN 2019
+//------------------------------------------------------------------------------
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 2.0 (the "License"); you may not use this file except
+// in compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-2.0.
+// Unless required by applicable law or agreed to in writing, software,
+// hardware and materials distributed under this License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+// or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//------------------------------------------------------------------------------
+
+`ifndef __WRTD_DEFINE_INCLUDED
+ `define __WRTD_DEFINE_INCLUDED
+
+ `define WRTD_MAX_CPUS 4
+ `define WRTD_MAX_DEVS 4
+
+ `define WRTD_ID_LEN 16
+
+ `define WRTD_IO_MSG_WORD_SIZE  3
+ `define WRTD_CFG_MSG_WORD_SIZE 5
+ `define WRTD_ROOT_WORD_SIZE    13
+ `define WRTD_RULE_WORD_SIZE    40
+ `define WRTD_ALRM_WORD_SIZE    15
+
+enum {
+      WRTD_ACTION_GET_CONFIG,
+      WRTD_ACTION_READW,
+      WRTD_ACTION_WRITEW
+} wrtd_trtl_actions;
+
+enum {
+      WRTD_DIR_INPUT,
+      WRTD_DIR_OUTPUT
+} wrtd_dir;
+
+class WrtdTstamp;
+   protected string   name;
+   protected uint32_t seconds;
+   protected uint32_t ns;
+   protected uint32_t frac;
+
+   function new ( uint32_t seconds = 0,
+		  uint32_t ns      = 0,
+		  uint32_t frac    = 0,
+		  string name      = "");
+      this.name = name;
+      set ( seconds, ns, frac );
+   endfunction // new
+
+   task mdisplay ( string str );
+      string tmp;
+      if (this.name == "")
+	tmp = $sformatf("<%t> %s", $realtime, str);
+      else
+	tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str);
+      $display (tmp);
+   endtask // mdisplay
+
+   function void set ( uint32_t seconds, uint32_t ns, uint32_t frac );
+      this.seconds = seconds;
+      this.ns      = ns;
+      this.frac    = frac;
+   endfunction // set
+
+   function void zero ( );
+      set ( 0, 0, 0);
+   endfunction // zero
+
+endclass // WrtdTstamp
+
+typedef struct {
+   uint32_t addr;
+   uint32_t nbr_alarms;
+   uint32_t alarms_addr;
+   uint32_t nbr_rules;
+   uint32_t rules_addr;
+   uint32_t nbr_devs;
+   uint32_t devs_addr[4];
+} wrtd_root;
+
+
+
+`endif //  `ifndef __WRTD_DEFINE_INCLUDED
--- a/hdl/testbench/include/wrtd_dev.svh
+++ b/hdl/testbench/include/wrtd_dev.svh
--- a/hdl/testbench/include/wrtd_rep_cap.svh
+++ b/hdl/testbench/include/wrtd_rep_cap.svh
--- a/hdl/testbench/include/wrtd_rule.svh
+++ b/hdl/testbench/include/wrtd_rule.svh
--- a/hdl/testbench/wrtd_ref_spec150t_adc/.gitignore
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/.gitignore
+work/
+NullFile
+Makefile
+modelsim.ini
+transcript*
+*.wlf
--- a/hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
--- a/hdl/testbench/wrtd_ref_spec150t_adc/README.md
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/README.md
+Introduction
+============
+
+This is a testbench for the SPEC150T-based FMC ADC WRTD reference design.
+
+Dependencies
+============
+
+To build this, you will need [hdl-make][1], using commit `968fa87` (or newer), as well as GNU Make.
+
+To run it, you will need Modelsim/Questa. It has been tested with Questa 10.5c on Linux.
+
+Build/Run Instrunctions
+=======================
+
+1. If not already done, pull all dependencies using `git submodule update --init` from within the
+   WRTD repository.
+2. Run `hdlmake` from this directory.
+3. Run `make` on the hdlmake-generated Makefile.
+4. Run `vsim -c -do run.do`.
+
+[1]: https://www.ohwr.org/projects/hdl-make/wiki
--- a/hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
--- a/hdl/testbench/wrtd_ref_spec150t_adc/main.sv
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/main.sv
--- a/hdl/testbench/wrtd_ref_spec150t_adc/run.do
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/run.do
--- a/hdl/testbench/wrtd_ref_spec150t_adc/synthesis_descriptor.vhd
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/synthesis_descriptor.vhd
--- a/hdl/testbench/list/.gitignore
+++ b/hdl/testbench/list/.gitignore
--- a/hdl/testbench/list/Manifest.py
+++ b/hdl/testbench/list/Manifest.py
--- a/hdl/testbench/list/list_driver.svh
+++ b/hdl/testbench/list/list_driver.svh
--- a/hdl/testbench/list/main.sv
+++ b/hdl/testbench/list/main.sv
--- a/hdl/testbench/list/run.do
+++ b/hdl/testbench/list/run.do
--- a/hdl/testbench/list/run_ci.do
+++ b/hdl/testbench/list/run_ci.do
--- a/hdl/testbench/list/synthesis_descriptor.vhd
+++ b/hdl/testbench/list/synthesis_descriptor.vhd
--- a/builder/hdl/top/spec_adc/Manifest.py
+++ b/builder/hdl/top/spec_adc/Manifest.py
--- a/hdl/top/wrtd_ref_spec150t_adc/carrier_csr.vhd
+++ b/hdl/top/wrtd_ref_spec150t_adc/carrier_csr.vhd
--- a/hdl/top/wrtd_ref_spec150t_adc/carrier_csr_wbgen2_pkg.vhd
+++ b/hdl/top/wrtd_ref_spec150t_adc/carrier_csr_wbgen2_pkg.vhd
--- a/hdl/top/wrtd_ref_spec150t_adc/dma_eic.vhd
+++ b/hdl/top/wrtd_ref_spec150t_adc/dma_eic.vhd
--- a/hdl/top/wrtd_ref_spec150t_adc/wb_gen/.gitignore
+++ b/hdl/top/wrtd_ref_spec150t_adc/wb_gen/.gitignore
+*
+!.gitignore
+!*.wb
+!Makefile
--- a/hdl/top/wrtd_ref_spec150t_adc/wb_gen/Makefile
+++ b/hdl/top/wrtd_ref_spec150t_adc/wb_gen/Makefile
--- a/builder/spec-lib/wb_gen/carrier_csr.wb
+++ b/builder/spec-lib/wb_gen/carrier_csr.wb
--- a/builder/spec-lib/wb_gen/dma_eic.wb
+++ b/builder/spec-lib/wb_gen/dma_eic.wb
--- a/builder/hdl/top/spec_adc/spec_adc_top.vhd
+++ b/builder/hdl/top/spec_adc/spec_adc_top.vhd
--- a/hdl/top/svec/list_tdc_fd/Manifest.py
+++ b/hdl/top/svec/list_tdc_fd/Manifest.py
--- a/hdl/top/svec/list_tdc_fd/svec_list_top.vhd
+++ b/hdl/top/svec/list_tdc_fd/svec_list_top.vhd
--- a/software/firmware/adc/wrtd-adcin.c
+++ b/software/firmware/adc/wrtd-adcin.c
--- a/software/stresstests/Makefile
+++ b/software/stresstests/Makefile
--- a/software/stresstests/wrtd-freqmeter.c
+++ b/software/stresstests/wrtd-freqmeter.c
--- a/software/stresstests/wrtd-timetest.c
+++ b/software/stresstests/wrtd-timetest.c
--- a/software/tools/wrtd-config.c
+++ b/software/tools/wrtd-config.c
--- a/software/tools/wrtd-in-config.c
+++ b/software/tools/wrtd-in-config.c
--- a/software/tools/wrtd-out-config.c
+++ b/software/tools/wrtd-out-config.c
--- a/software/unittest/.gitignore
+++ b/software/unittest/.gitignore
-wrtd-ut
--- a/software/unittest/CuTest.c
+++ b/software/unittest/CuTest.c
--- a/software/unittest/CuTest.h
+++ b/software/unittest/CuTest.h
--- a/software/unittest/Makefile
+++ b/software/unittest/Makefile
--- a/software/unittest/wrtd-ut-common.c
+++ b/software/unittest/wrtd-ut-common.c
--- a/software/unittest/wrtd-ut-input.c
+++ b/software/unittest/wrtd-ut-input.c
--- a/software/unittest/wrtd-ut-op.c
+++ b/software/unittest/wrtd-ut-op.c
--- a/software/unittest/wrtd-ut-output.c
+++ b/software/unittest/wrtd-ut-output.c
--- a/software/unittest/wrtd-ut.c
+++ b/software/unittest/wrtd-ut.c
--- a/software/unittest/wrtd-ut.h
+++ b/software/unittest/wrtd-ut.h
--- a/tests/firmware/.gitignore
+++ b/tests/firmware/.gitignore
--- a/tests/firmware/Makefile
+++ b/tests/firmware/Makefile
--- a/tests/firmware/rmq-udp/Kconfig
+++ b/tests/firmware/rmq-udp/Kconfig
--- a/tests/firmware/rmq-udp/Makefile
+++ b/tests/firmware/rmq-udp/Makefile
--- a/tests/firmware/rmq-udp/configs/mt_defconfig
+++ b/tests/firmware/rmq-udp/configs/mt_defconfig
--- a/tests/firmware/rmq-udp/rmq-udp.c
+++ b/tests/firmware/rmq-udp/rmq-udp.c
--- a/tools/hdl-gen/README.md
+++ b/tools/hdl-gen/README.md
--- a/builder/fmc-adc-100m14b4cha-spec/config.yaml
+++ b/builder/fmc-adc-100m14b4cha-spec/config.yaml
--- a/builder/fmc-adc-100m14b4cha-spec/repo.txt
+++ b/builder/fmc-adc-100m14b4cha-spec/repo.txt
--- a/builder/fmc-adc-100m14b4cha-spec/spec-fmc0.ucf
+++ b/builder/fmc-adc-100m14b4cha-spec/spec-fmc0.ucf
--- a/builder/fmc-adc-100m14b4cha-spec/top.vhd
+++ b/builder/fmc-adc-100m14b4cha-spec/top.vhd
--- a/builder/fmc-adc-100m14b4cha-svec/config.yaml
+++ b/builder/fmc-adc-100m14b4cha-svec/config.yaml
--- a/builder/fmc-adc-100m14b4cha-svec/repo.txt
+++ b/builder/fmc-adc-100m14b4cha-svec/repo.txt
--- a/builder/fmc-adc-100m14b4cha-svec/svec-fmc0.ucf
+++ b/builder/fmc-adc-100m14b4cha-svec/svec-fmc0.ucf
--- a/builder/fmc-adc-100m14b4cha-svec/svec-fmc1.ucf
+++ b/builder/fmc-adc-100m14b4cha-svec/svec-fmc1.ucf
--- a/builder/fmc-adc-100m14b4cha-svec/top.vhd
+++ b/builder/fmc-adc-100m14b4cha-svec/top.vhd
--- a/builder/fmc-delay-1ns-8cha/repo.txt
+++ b/builder/fmc-delay-1ns-8cha/repo.txt
--- a/builder/fmc-delay-1ns-8cha/svec-fmc0.ucf
+++ b/builder/fmc-delay-1ns-8cha/svec-fmc0.ucf
--- a/builder/fmc-delay-1ns-8cha/svec-fmc1.ucf
+++ b/builder/fmc-delay-1ns-8cha/svec-fmc1.ucf
--- a/builder/fmc-delay-1ns-8cha/top.vhd
+++ b/builder/fmc-delay-1ns-8cha/top.vhd
--- a/builder/fmc-tdc-1ns-5cha/repo.txt
+++ b/builder/fmc-tdc-1ns-5cha/repo.txt
--- a/builder/fmc-tdc-1ns-5cha/svec-fmc0.ucf
+++ b/builder/fmc-tdc-1ns-5cha/svec-fmc0.ucf
--- a/builder/fmc-tdc-1ns-5cha/svec-fmc1.ucf
+++ b/builder/fmc-tdc-1ns-5cha/svec-fmc1.ucf
--- a/builder/fmc-tdc-1ns-5cha/top.vhd
+++ b/builder/fmc-tdc-1ns-5cha/top.vhd
--- a/builder/spec-lib/carrier_csr.vhd
+++ b/builder/spec-lib/carrier_csr.vhd
--- a/builder/spec-lib/carrier_csr_wbgen2_pkg.vhd
+++ b/builder/spec-lib/carrier_csr_wbgen2_pkg.vhd
--- a/builder/spec-lib/dma_eic.vhd
+++ b/builder/spec-lib/dma_eic.vhd
--- a/builder/spec-lib/wb_gen/Makefile
+++ b/builder/spec-lib/wb_gen/Makefile
--- a/builder/spec-lib/wb_gen/carrier_csr.h
+++ b/builder/spec-lib/wb_gen/carrier_csr.h
--- a/builder/spec-lib/wb_gen/carrier_csr.htm
+++ b/builder/spec-lib/wb_gen/carrier_csr.htm
--- a/tools/hdl-gen/builder/spec-lib/wb_gen/carrier_csr.wb
+++ b/tools/hdl-gen/builder/spec-lib/wb_gen/carrier_csr.wb
--- a/builder/spec-lib/wb_gen/dma_eic.h
+++ b/builder/spec-lib/wb_gen/dma_eic.h
--- a/builder/spec-lib/wb_gen/dma_eic.htm
+++ b/builder/spec-lib/wb_gen/dma_eic.htm
--- a/tools/hdl-gen/builder/spec-lib/wb_gen/dma_eic.wb
+++ b/tools/hdl-gen/builder/spec-lib/wb_gen/dma_eic.wb
--- a/builder/spec/Manifest-syn.py
+++ b/builder/spec/Manifest-syn.py
--- a/builder/spec/Manifest-top.py
+++ b/builder/spec/Manifest-top.py
--- a/builder/spec/syn_extra_steps.tcl
+++ b/builder/spec/syn_extra_steps.tcl
--- a/builder/spec/top.ucf
+++ b/builder/spec/top.ucf
--- a/builder/spec/top.vhd
+++ b/builder/spec/top.vhd
--- a/builder/svec/Manifest-syn.py
+++ b/builder/svec/Manifest-syn.py
--- a/builder/svec/Manifest-top.py
+++ b/builder/svec/Manifest-top.py
--- a/builder/svec/syn_extra_steps.tcl
+++ b/builder/svec/syn_extra_steps.tcl
--- a/builder/svec/top.ucf
+++ b/builder/svec/top.ucf
--- a/builder/svec/top.vhd
+++ b/builder/svec/top.vhd
--- a/builder/wrtd_builder.py
+++ b/builder/wrtd_builder.py
--- a/configs/adc.yaml
+++ b/configs/adc.yaml
--- a/configs/fd_tdc.yaml
+++ b/configs/fd_tdc.yaml
--- a/configs/spec_adc.yaml
+++ b/configs/spec_adc.yaml
--- a/configs/tdc.yaml
+++ b/configs/tdc.yaml
--- a/configs/tdc_fd.yaml
+++ b/configs/tdc_fd.yaml