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White Rabbit Trigger Distribution
Commit 0b04e115 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: update dependencies

parent 53772dc3
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Showing with 21 additions and 17 deletions
general-cores @ a472d47f
Subproject commit 8d4e5c18c6f80f1c1c588bb9000c45da656788cd
Subproject commit a472d47fde3bbeb4a51b98681922d7134b2758e2
gn4124-core @ 6c4dca2c
Subproject commit c9d96ee08abce9440ec79e5d2c11359876ddb486
Subproject commit 6c4dca2cad82db1064972a8f0ee7aa80aa6d5d42
mock-turtle @ 6794030e
Subproject commit d7779597eee20a31f470f0cb993f104c72a9d090
Subproject commit 6794030e19c0e86ae5d3c0908b2f3797d951cb98
wr-cores @ acd8e81c
Subproject commit 4f1fafd72b08dee6ea9ef13715e6e9981e5d5021
Subproject commit acd8e81ca573703fe4a530e016a79b9f5760c0e2
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @ 0b04e115
......@@ -211,8 +211,8 @@ NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
# IOBs
#----------------------------------------
INST "cmp_gn4124_core/cmp_wrapped_gn4124/l2p_rdy_t" IOB = FALSE;
INST "cmp_gn4124_core/cmp_wrapped_gn4124/l_wr_rdy_t*" IOB = FALSE;
INST "cmp_gn4124_core/cmp_wrapped_gn4124/cmp_sync_l2p_rdy/sync0" IOB = FALSE;
#INST "cmp_gn4124_core/cmp_wrapped_gn4124/l_wr_rdy_i*" IOB = FALSE;
NET "fmc?_adc_gpio*" IOB = FALSE;
......
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ 0b04e115
......@@ -217,8 +217,9 @@ architecture arch of wrtd_ref_spec150t_adc is
-----------------------------------------------------------------------------
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_px_pll_cfg := (
enabled => TRUE, divide => 3, multiply => 8 );
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
-- SPEC carrier CSR constants
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
......@@ -373,7 +374,9 @@ architecture arch of wrtd_ref_spec150t_adc is
signal clk_ref_125m : std_logic;
signal sys_clk_pll_locked : std_logic;
signal clk_ddr_333m : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
signal rst_ddr_333m_n : std_logic := '0';
......@@ -774,7 +777,7 @@ begin -- architecture arch
g_VERBOSE => FALSE,
g_WITH_EXTERNAL_CLOCK_INPUT => FALSE,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_PLL_CONFIG => c_WRPC_PLL_CONFIG,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_FABRIC_IFACE => PLAIN)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
......@@ -786,10 +789,10 @@ begin -- architecture arch
areset_edge_n_i => gn_rst_n_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_ddr_333m,
clk_pll_aux_o => clk_pll_aux,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_ddr_333m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_sync_n_o,
......@@ -817,12 +820,10 @@ begin -- architecture arch
flash_miso_i => spi_miso_i,
wb_slave_o => cnx_slave_out(c_WB_SLAVE_WRC),
wb_slave_i => cnx_slave_in(c_WB_SLAVE_WRC),
wrf_src_o => eth_rx_in,
wrf_src_i => eth_rx_out,
wrf_snk_o => eth_tx_in,
wrf_snk_i => eth_tx_out,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
......@@ -833,6 +834,9 @@ begin -- architecture arch
led_act_o => wr_led_act,
link_ok_o => wrabbit_en);
clk_ddr_333m <= clk_pll_aux(0);
rst_ddr_333m_n <= rst_pll_aux_n(0);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
......
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