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White Rabbit Trigger Distribution
Commit 1037cd98 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] update spec template and fix gennum irq pin location

parent c2a0c4e2
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spec @ ff41468d
Subproject commit 270ca1d9e0a21a6c6af0772445bf6984150b0704 Subproject commit ff41468d28db8a6609f0d8aa26f6f6c160635661
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @ 1037cd98
...@@ -61,8 +61,8 @@ NET "gn_p_rd_d_rdy_i[0]" LOC = N16; ...@@ -61,8 +61,8 @@ NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_tx_error_i" LOC = M17; NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[1]" LOC = B22; NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_vc_rdy_i[0]" LOC = B21; NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_gpio_b[1]" LOC = U16; NET "gn_gpio_b[1]" LOC = AB19;
NET "gn_gpio_b[0]" LOC = AB19; NET "gn_gpio_b[0]" LOC = U16;
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18"; NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_?_i" IOSTANDARD = "DIFF_SSTL18_I"; NET "gn_p2l_clk_?_i" IOSTANDARD = "DIFF_SSTL18_I";
...@@ -210,28 +210,25 @@ NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25"; ...@@ -210,28 +210,25 @@ NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
#=============================================================================== #===============================================================================
# Timing constraints and exceptions # Timing constraints and exceptions
#=============================================================================== #===============================================================================
# All input clocks # All input clocks
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_in;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_in;
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_pllref_in" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i; NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%; NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp;
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i"; NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%; TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "*cmp_xwrc_board_spec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "gn_p2l_clk_p_i" TNM_NET = "p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk"; NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
TIMESPEC TS_p2l_clk = PERIOD "p2l_clk" 5 ns HIGH 50%; TIMESPEC TS_p2l_clk = PERIOD "p2l_clk" 5 ns HIGH 50%;
#---------------------------------------- #----------------------------------------
# WR DMTD tweaks # WR DMTD tweaks
#---------------------------------------- #----------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit; INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit; INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
...@@ -257,11 +254,10 @@ NET "cmp_spec_template_wr/clk_ref_125m" TNM_NET = clk_125m_pllref; ...@@ -257,11 +254,10 @@ NET "cmp_spec_template_wr/clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "cmp_spec_template_wr/clk_ddr_333m" TNM_NET = ddr_clk_333m; NET "cmp_spec_template_wr/clk_ddr_333m" TNM_NET = ddr_clk_333m;
NET "*cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd; NET "*cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk; NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk; NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk; NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref"; TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk";
# Exceptions for crossings via gc_sync_ffs # Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs"; NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
......
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @ 1037cd98
...@@ -291,16 +291,16 @@ module dut_env ...@@ -291,16 +291,16 @@ module dut_env
initial begin initial begin
// Skip WR SoftPLL lock // Skip WR SoftPLL lock
force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_spec_template_wr.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111; WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE // Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_spec_template_wr.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0; multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_spec_template_wr.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0; multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_spec_template_wr.g_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core. force DUT.cmp_spec_template_wr.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu. WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0; multiplier.D3.OPMODE_dly = 0;
end // initial begin end // initial begin
......
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ 1037cd98
...@@ -105,8 +105,8 @@ entity wrtd_ref_spec150t_adc is ...@@ -105,8 +105,8 @@ entity wrtd_ref_spec150t_adc is
------------------------------------------ ------------------------------------------
-- GN4124 interface -- GN4124 interface
-- --
-- gn_gpio_b[0] -> AB19 -> GN4124 GPIO9 -- gn_gpio_b[1] -> AB19 -> GN4124 GPIO9
-- gn_gpio_b[1] -> U16 -> GN4124 GPIO8 -- gn_gpio_b[0] -> U16 -> GN4124 GPIO8
------------------------------------------ ------------------------------------------
gn_rst_n_i : in std_logic; gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic; gn_p2l_clk_n_i : in std_logic;
......
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