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White Rabbit Trigger Distribution
Commits
28f4ea27
Commit
28f4ea27
authored
Mar 12, 2019
by
Dimitris Lampridis
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sim: add basic supporting for accessing the wrtd logs
parent
639eef6a
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4 changed files
with
153 additions
and
34 deletions
+153
-34
mock-turtle
dependencies/mock-turtle
+1
-1
wrtd_definitions.svh
hdl/testbench/include/wrtd_definitions.svh
+43
-12
wrtd_driver.svh
hdl/testbench/include/wrtd_driver.svh
+98
-10
main.sv
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
+11
-11
No files found.
mock-turtle
@
f3013290
Subproject commit
6beecf5aa562e81a1170af4edbfb59b49245bfb3
Subproject commit
f30132905e64f360372278fee7f07c60f60b97e6
hdl/testbench/include/wrtd_definitions.svh
View file @
28f4ea27
...
@@ -47,6 +47,44 @@ enum {
...
@@ -47,6 +47,44 @@ enum {
WRTD_ACTION_WRITEW
WRTD_ACTION_WRITEW
}
wrtd_trtl_actions
;
}
wrtd_trtl_actions
;
`define
WRTD_ACTION_LOG
'
h20
typedef
enum
uint32_t
{
WRTD_LOG_MSG_EV_GENERATED
=
0
,
WRTD_LOG_MSG_EV_CONSUMED
,
WRTD_LOG_MSG_EV_DISCARDED
,
WRTD_LOG_MSG_EV_NETWORK
,
WRTD_LOG_MSG_LINK
}
wrtd_log_msg_type
;
typedef
enum
uint32_t
{
WRTD_LOG_GENERATED_ALARM
=
1
,
WRTD_LOG_GENERATED_DEVICE_0
=
8
,
WRTD_LOG_GENERATED_DEVICE_1
=
16
,
WRTD_LOG_GENERATED_DEVICE_2
=
24
,
WRTD_LOG_GENERATED_DEVICE_3
=
32
,
WRTD_LOG_GENERATED_DEVICE_4
=
40
,
WRTD_LOG_GENERATED_DEVICE_5
=
48
,
WRTD_LOG_GENERATED_DEVICE_6
=
56
,
WRTD_LOG_GENERATED_DEVICE_7
=
64
}
wrtd_log_gen_reason
;
typedef
enum
uint32_t
{
WRTD_LOG_CONSUMED_START
=
1
,
WRTD_LOG_CONSUMED_DONE
}
wrtd_log_con_reason
;
typedef
enum
uint32_t
{
WRTD_LOG_DISCARD_NO_SYNC
=
1
,
WRTD_LOG_DISCARD_TIMEOUT
,
WRTD_LOG_DISCARD_OVERFLOW
}
wrtd_log_dsc_reason
;
typedef
enum
uint32_t
{
WRTD_LOG_NETWORK_TX
=
1
,
WRTD_LOG_NETWORK_RX
}
wrtd_log_net_reason
;
enum
{
enum
{
WRTD_DIR_INPUT
,
WRTD_DIR_INPUT
,
WRTD_DIR_OUTPUT
WRTD_DIR_OUTPUT
...
@@ -66,21 +104,10 @@ class WrtdTstamp;
...
@@ -66,21 +104,10 @@ class WrtdTstamp;
function
new
(
uint32_t
seconds
=
0
,
function
new
(
uint32_t
seconds
=
0
,
uint32_t
ns
=
0
,
uint32_t
ns
=
0
,
uint32_t
frac
=
0
,
uint32_t
frac
=
0
)
;
string
name
=
""
)
;
this
.
name
=
name
;
set
(
seconds
,
ns
,
frac
)
;
set
(
seconds
,
ns
,
frac
)
;
endfunction
// new
endfunction
// new
task
mdisplay
(
string
str
)
;
string
tmp
;
if
(
this
.
name
==
""
)
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
else
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
$
display
(
tmp
)
;
endtask
// mdisplay
function
void
set
(
uint32_t
seconds
,
uint32_t
ns
,
uint32_t
frac
)
;
function
void
set
(
uint32_t
seconds
,
uint32_t
ns
,
uint32_t
frac
)
;
this
.
seconds
=
seconds
;
this
.
seconds
=
seconds
;
this
.
ns
=
ns
;
this
.
ns
=
ns
;
...
@@ -117,6 +144,10 @@ class WrtdTstamp;
...
@@ -117,6 +144,10 @@ class WrtdTstamp;
set
(
0
,
0
,
0
)
;
set
(
0
,
0
,
0
)
;
endfunction
// zero
endfunction
// zero
function
string
tostring
(
)
;
return
$
sformatf
(
"%0d:%0d.%0d"
,
this
.
seconds
,
this
.
ns
,
this
.
frac
)
;
endfunction
;
// tostring
endclass
// WrtdTstamp
endclass
// WrtdTstamp
class
WrtdId
;
class
WrtdId
;
...
...
hdl/testbench/include/wrtd_driver.svh
View file @
28f4ea27
...
@@ -34,6 +34,7 @@
...
@@ -34,6 +34,7 @@
class
WrtdDrv
;
class
WrtdDrv
;
uint32_t
ready
;
uint32_t
ready
;
protected
string
name
;
protected
string
name
;
protected
byte
unsigned
enable_logging
;
protected
MockTurtleDriver
mt
;
protected
MockTurtleDriver
mt
;
protected
uint32_t
nbr_cpus
;
protected
uint32_t
nbr_cpus
;
protected
uint32_t
free_rule_slots
[]
;
protected
uint32_t
free_rule_slots
[]
;
...
@@ -45,9 +46,15 @@ class WrtdDrv;
...
@@ -45,9 +46,15 @@ class WrtdDrv;
protected
WrtdRepCapCollection
alarms
;
protected
WrtdRepCapCollection
alarms
;
function
new
(
CBusAccessor
acc
,
uint64_t
base
,
function
new
(
CBusAccessor
acc
,
uint64_t
base
,
vIMockTurtleIRQ
irq
,
string
name
=
""
)
;
vIMockTurtleIRQ
irq
,
string
name
=
""
,
byte
unsigned
enable_logging
=
1
)
;
this
.
name
=
name
;
this
.
name
=
name
;
this
.
mt
=
new
(
acc
,
base
,
irq
,
name
)
;
this
.
mt
=
new
(
acc
,
base
,
irq
,
name
)
;
this
.
enable_logging
=
enable_logging
;
endfunction
// new
endfunction
// new
task
mdisplay
(
string
str
)
;
task
mdisplay
(
string
str
)
;
...
@@ -146,6 +153,9 @@ class WrtdDrv;
...
@@ -146,6 +153,9 @@ class WrtdDrv;
this
.
roots
[
i
]
.
alarms_addr
=
data
[
9
]
;
this
.
roots
[
i
]
.
alarms_addr
=
data
[
9
]
;
// init free rule slots
// init free rule slots
this
.
free_rule_slots
[
i
]
=
this
.
roots
[
i
]
.
nbr_rules
;
this
.
free_rule_slots
[
i
]
=
this
.
roots
[
i
]
.
nbr_rules
;
// turn on all logging if enabled
if
(
this
.
enable_logging
)
msg_writew
(
i
,
this
.
roots
[
i
]
.
addr
+
12
,
1
,
{
data
[
3
]
|
32'hff
}
)
;
end
end
// initialise rules
// initialise rules
...
@@ -412,17 +422,95 @@ class WrtdDrv;
...
@@ -412,17 +422,95 @@ class WrtdDrv;
msg_writew
(
core
,
addr
,
`WRTD_ALRM_WORD_SIZE
,
data
)
;
msg_writew
(
core
,
addr
,
`WRTD_ALRM_WORD_SIZE
,
data
)
;
endtask
// write_alarm
endtask
// write_alarm
task
log_read
(
)
;
function
string
log_msg_tostring
(
MQueueMsg
msg
)
;
endtask
// log_read
string
ret
;
wrtd_log_msg_type
msg_type
;
wrtd_log_gen_reason
gen_reason
;
wrtd_log_con_reason
con_reason
;
wrtd_log_dsc_reason
dsc_reason
;
wrtd_log_net_reason
net_reason
;
WrtdTstamp
ev_tstamp
,
msg_tstamp
;
WrtdId
ev_id
;
ret
=
""
;
if
(
msg
.
header
.
msg_id
!=
`WRTD_ACTION_LOG
)
begin
$
error
(
"log_msg_tostring: unknown message id %.8x"
,
msg
.
header
.
msg_id
)
;
return
ret
;
end
msg_tstamp
=
new
()
;
msg_tstamp
.
data_unpack
(
msg
.
data
[
11
:
13
]
)
;
ret
=
{
ret
,
$
sformatf
(
"log timestamp: %s"
,
msg_tstamp
.
tostring
()
)
};
ev_tstamp
=
new
()
;
ev_tstamp
.
data_unpack
(
msg
.
data
[
2
:
4
]
)
;
ret
=
{
ret
,
$
sformatf
(
", event timestamp: %s"
,
ev_tstamp
.
tostring
()
)
};
ev_id
=
new
()
;
ev_id
.
data_unpack
(
msg
.
data
[
5
:
8
]
)
;
ret
=
{
ret
,
$
sformatf
(
", id: %s, seq: %0d"
,
ev_id
.
get
()
,
msg
.
data
[
9
]
)
};
$
cast
(
msg_type
,
msg
.
data
[
0
]
)
;
ret
=
{
ret
,
$
sformatf
(
", log type: %s"
,
msg_type
.
name
()
)
};
case
(
msg_type
)
WRTD_LOG_MSG_EV_GENERATED
:
begin
$
cast
(
gen_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
gen_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_CONSUMED
:
begin
$
cast
(
con_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
con_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_DISCARDED
:
begin
$
cast
(
dsc_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
dsc_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_NETWORK
:
begin
$
cast
(
net_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
net_reason
.
name
()
)
};
end
endcase
;
// case ( msg_type )
return
ret
;
endfunction
// log_msg_tostring
task
check_logs
(
)
;
int
i
;
MQueueMsg
msg
;
for
(
int
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
begin
while
(
mt
.
hmq_pending_messages
(
i
,
0
)
)
begin
msg
=
new
(
i
,
0
)
;
mt
.
hmq_peek_message
(
msg
)
;
if
(
msg
.
header
.
msg_id
!=
`WRTD_ACTION_LOG
)
break
;
mt
.
hmq_receive_message
(
msg
)
;
mdisplay
(
$
sformatf
(
"LOG MSG from core %0d: %s"
,
i
,
log_msg_tostring
(
msg
)
)
)
;
end
end
endtask
// check_logs
task
update
(
)
;
task
update
(
)
;
mt
.
update
(
)
;
mt
.
update
(
)
;
fork
if
(
this
.
enable_logging
)
/* -----\/----- EXCLUDED -----\/-----
check_logs
(
)
;
check_log_queue ( 0 );
check_log_queue ( 1 );
-----/\----- EXCLUDED -----/\----- */
join
endtask
// update
endtask
// update
endclass
// WrtdDrv
endclass
// WrtdDrv
...
...
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @
28f4ea27
...
@@ -93,7 +93,7 @@ module main;
...
@@ -93,7 +93,7 @@ module main;
if
(
val
!=
expected
)
if
(
val
!=
expected
)
$
fatal
(
1
,
"ADC status error (got 0x%8x, expected 0x%8x)."
,
val
,
expected
)
;
$
fatal
(
1
,
"ADC status error (got 0x%8x, expected 0x%8x)."
,
val
,
expected
)
;
$
display
(
"
<%t> DUTA
ADC configured and armed"
,
$
realtime
)
;
$
display
(
"
[DUT:A] <%t>
ADC configured and armed"
,
$
realtime
)
;
wait
(
duta_acq_state
==
1
)
;
wait
(
duta_acq_state
==
1
)
;
end
end
...
@@ -103,7 +103,7 @@ module main;
...
@@ -103,7 +103,7 @@ module main;
devB
=
new
(
accB
,
MT_BASE
,
MtIrqMonitorB
,
"DUT:B"
)
;
devB
=
new
(
accB
,
MT_BASE
,
MtIrqMonitorB
,
"DUT:B"
)
;
devB
.
init
()
;
devB
.
init
()
;
devB
.
add_rule
(
"rule0"
)
;
devB
.
add_rule
(
"rule0"
)
;
devB
.
set_rule
(
"rule0"
,
"NET0"
,
"ADCO1"
,
10
0000
)
;
devB
.
set_rule
(
"rule0"
,
"NET0"
,
"ADCO1"
,
5
0000
)
;
devB
.
enable_rule
(
"rule0"
)
;
devB
.
enable_rule
(
"rule0"
)
;
// Config DUTB to trigger on WRTD and get 64 samples
// Config DUTB to trigger on WRTD and get 64 samples
...
@@ -127,16 +127,16 @@ module main;
...
@@ -127,16 +127,16 @@ module main;
if
(
val
!=
expected
)
if
(
val
!=
expected
)
$
fatal
(
1
,
"ADC status error (got 0x%8x, expected 0x%8x)."
,
val
,
expected
)
;
$
fatal
(
1
,
"ADC status error (got 0x%8x, expected 0x%8x)."
,
val
,
expected
)
;
$
display
(
"
<%t> DUTB
ADC configured and armed"
,
$
realtime
)
;
$
display
(
"
[DUT:B] <%t>
ADC configured and armed"
,
$
realtime
)
;
wait
(
dutb_acq_state
==
1
)
;
wait
(
dutb_acq_state
==
1
)
;
end
end
join
join
#
50u
s
;
#
50u
s
;
$
display
(
"
<%t> DUTB
START ACQ 1"
,
$
realtime
)
;
$
display
(
"
[DUT:B] <%t>
START ACQ 1"
,
$
realtime
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CTL
,
'h00000001
)
;
// FSM start
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CTL
,
'h00000001
)
;
// FSM start
$
display
(
"
<%t> DUTA
START ACQ 1"
,
$
realtime
)
;
$
display
(
"
[DUT:A] <%t>
START ACQ 1"
,
$
realtime
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CTL
,
'h00000001
)
;
// FSM start
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CTL
,
'h00000001
)
;
// FSM start
#
5u
s
;
#
5u
s
;
...
@@ -147,10 +147,10 @@ module main;
...
@@ -147,10 +147,10 @@ module main;
fork
fork
begin
begin
wait
(
duta_acq_state
==
1
)
;
wait
(
duta_acq_state
==
1
)
;
$
display
(
"
<%t> DUTA
END ACQ 1"
,
$
realtime
)
;
$
display
(
"
[DUT:A] <%t>
END ACQ 1"
,
$
realtime
)
;
accA
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_POS
,
val
)
;
accA
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_POS
,
val
)
;
$
display
(
"<%t> DUTA
TRIG POSITION %.8x"
,
$
realtime
,
val
)
;
$
display
(
"[DUT:A] <%t>
TRIG POSITION %.8x"
,
$
realtime
,
val
)
;
// DMA transfer
// DMA transfer
accA
.
write
(
'h2008
,
val
)
;
// dma start addr
accA
.
write
(
'h2008
,
val
)
;
// dma start addr
...
@@ -168,15 +168,15 @@ module main;
...
@@ -168,15 +168,15 @@ module main;
accA
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
accA
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
wait
(
DUTA
.
DUT
.
dma_irq
[
0
]
==
1
)
;
wait
(
DUTA
.
DUT
.
dma_irq
[
0
]
==
1
)
;
$
display
(
"
<%t> DUTA
END DMA 1"
,
$
realtime
)
;
$
display
(
"
[DUT:A] <%t>
END DMA 1"
,
$
realtime
)
;
end
end
begin
begin
wait
(
dutb_acq_state
==
1
)
;
wait
(
dutb_acq_state
==
1
)
;
$
display
(
"
<%t> DUTB
END ACQ 1"
,
$
realtime
)
;
$
display
(
"
[DUT:B] <%t>
END ACQ 1"
,
$
realtime
)
;
accB
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_POS
,
val
)
;
accB
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_POS
,
val
)
;
$
display
(
"<%t> DUTB
TRIG POSITION %.8x"
,
$
realtime
,
val
)
;
$
display
(
"[DUT:B] <%t>
TRIG POSITION %.8x"
,
$
realtime
,
val
)
;
// DMA transfer
// DMA transfer
accB
.
write
(
'h2008
,
val
)
;
// dma start addr
accB
.
write
(
'h2008
,
val
)
;
// dma start addr
...
@@ -194,7 +194,7 @@ module main;
...
@@ -194,7 +194,7 @@ module main;
accB
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
accB
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
wait
(
DUTB
.
DUT
.
dma_irq
[
0
]
==
1
)
;
wait
(
DUTB
.
DUT
.
dma_irq
[
0
]
==
1
)
;
$
display
(
"
<%t> DUTB
END DMA 1"
,
$
realtime
)
;
$
display
(
"
[DUT:B] <%t>
END DMA 1"
,
$
realtime
)
;
end
end
join
join
...
...
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