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White Rabbit Trigger Distribution
Commit 47a61400 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: cleanup tab characters in simulations

parent 8c8e6bf0
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hdl/testbench/include/wrtd_definitions.svh
View file @ 47a61400
......@@ -111,8 +111,8 @@ class WrtdTstamp;
protected uint32_t frac;
function new ( uint32_t seconds = 0,
uint32_t ns = 0,
uint32_t frac = 0 );
uint32_t ns = 0,
uint32_t frac = 0 );
set ( seconds, ns, frac );
endfunction // new
......@@ -172,12 +172,12 @@ class WrtdId;
function void set ( string id );
if ( id.len() > `WRTD_ID_LEN )
$error ( "length of string longer than the available storage" );
$error ( "length of string longer than the available storage" );
else
begin
this.clear();
this.id = id;
end
begin
this.clear();
this.id = id;
end
endfunction // set
function string get ( );
......@@ -189,17 +189,17 @@ class WrtdId;
wrtd_data d;
d = new[`WRTD_ID_LEN / 4];
for ( i = 0; i < `WRTD_ID_LEN / 4; i ++ )
d[i] = 0;
d[i] = 0;
for ( i = 0; i < this.id.len(); i ++ )
d[i/4] |= this.id[i] << ( 8 * ( i % 4 ) );
d[i/4] |= this.id[i] << ( 8 * ( i % 4 ) );
return d;
endfunction // data_pack
function void data_unpack ( wrtd_data data );
if ( data.size() > `WRTD_ID_LEN / 4 )
$error ( "length of data longer than the available storage" );
$error ( "length of data longer than the available storage" );
else
this.id = { <<32 { { <<8 { data } } } };
this.id = { <<32 { { <<8 { data } } } };
endfunction // data_unpack
function int is_empty ( );
......
hdl/testbench/include/wrtd_driver.svh
View file @ 47a61400
This diff is collapsed.
hdl/testbench/include/wrtd_rep_cap.svh
View file @ 47a61400
......@@ -47,9 +47,9 @@ virtual class WrtdRepCap;
task mdisplay ( string str );
string tmp;
if (this.name == "")
tmp = $sformatf("<%t> %s", $realtime, str);
tmp = $sformatf("<%t> %s", $realtime, str);
else
tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str);
tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str);
$display (tmp);
endtask // mdisplay
......@@ -83,9 +83,9 @@ virtual class WrtdRepCap;
function void set_enable ( int enable );
if ( enable > 0)
this.enabled = 1;
this.enabled = 1;
else
this.enabled = 0;
this.enabled = 0;
endfunction // set_enable
function void set_disable ( );
......@@ -110,17 +110,17 @@ class WrtdRepCapCollection;
task mdisplay ( string str );
string tmp;
if (this.name == "")
tmp = $sformatf("<%t> %s", $realtime, str);
tmp = $sformatf("<%t> %s", $realtime, str);
else
tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str);
tmp = $sformatf("[%s] <%t> %s", this.name, $realtime, str);
$display (tmp);
endtask // mdisplay
function void validate_id ( string rep_cap_id );
if ( rep_cap_id.len() > `WRTD_ID_LEN )
$error ( "repeated capability name '%s' is too long", rep_cap_id );
$error ( "repeated capability name '%s' is too long", rep_cap_id );
if ( rep_cap_id.len() == 0 )
$error ( "repeated capability name is null" );
$error ( "repeated capability name is null" );
endfunction // validate_id
function int add ( string rep_cap_id );
......@@ -131,21 +131,21 @@ class WrtdRepCapCollection;
idx = -1;
for ( i = 0; i < this.collection.size(); i++ )
begin
begin
if ( this.collection[i].match ( rep_cap_id ) )
begin
$error ( "'%s' repeated capability ID already exists", rep_cap_id );
return -1;
end
if ( idx == -1 && this.collection[i].is_free() )
idx = i;
end
if ( this.collection[i].match ( rep_cap_id ) )
begin
$error ( "'%s' repeated capability ID already exists", rep_cap_id );
return -1;
end
if ( idx == -1 && this.collection[i].is_free() )
idx = i;
end
if ( idx == -1 )
$error ( "cannot add '%s' repeated capability, no space available", rep_cap_id );
$error ( "cannot add '%s' repeated capability, no space available", rep_cap_id );
else
this.collection[idx].set_rep_cap_id ( rep_cap_id );
this.collection[idx].set_rep_cap_id ( rep_cap_id );
return idx;
endfunction // add
......@@ -156,8 +156,8 @@ class WrtdRepCapCollection;
validate_id ( rep_cap_id );
for ( i = 0; i < this.collection.size(); i++ )
if ( this.collection[i].match ( rep_cap_id ) )
return i;
if ( this.collection[i].match ( rep_cap_id ) )
return i;
return -1;
endfunction // find
......@@ -168,15 +168,15 @@ class WrtdRepCapCollection;
idx = find ( rep_cap_id );
if ( idx == -1 )
begin
$error ( "%s repeated capability ID cannot be removed because it does not exist", rep_cap_id );
return idx;
end
begin
$error ( "%s repeated capability ID cannot be removed because it does not exist", rep_cap_id );
return idx;
end
if ( this.collection[idx].is_enabled ( ) )
$error ( "%s repeated capability ID cannot be removed because it is enabled", rep_cap_id );
$error ( "%s repeated capability ID cannot be removed because it is enabled", rep_cap_id );
else
this.collection[idx].clear();
this.collection[idx].clear();
return idx;
endfunction // remove
......
hdl/testbench/include/wrtd_rule.svh
View file @ 47a61400
......@@ -38,7 +38,7 @@ class WrtdRule extends WrtdRepCap;
protected uint32_t hold_off_ns;
protected uint32_t resync_period_ns;
protected uint32_t resync_factor;
int hash_chain;
int hash_chain;
protected uint32_t rx_events;
protected WrtdTstamp rx_last;
protected uint32_t tx_events;
......
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @ 47a61400
......@@ -226,14 +226,14 @@ module dut_env
gc_sfp_i2c_adapter
SFP_I2C
(
.clk_i (clk_125m_pll),
.rst_n_i (1'b1),
.scl_i (sfp_scl),
.sda_i (sfp_sda),
.sda_en_o (sfp_sda_en),
.sfp_det_valid_i (1'b1),
.sfp_data_i (128'h0123456789ABCDEF0123456789ABCDEF)
);
.clk_i (clk_125m_pll),
.rst_n_i (1'b1),
.scl_i (sfp_scl),
.sda_i (sfp_sda),
.sda_en_o (sfp_sda_en),
.sfp_det_valid_i (1'b1),
.sfp_data_i (128'h0123456789ABCDEF0123456789ABCDEF)
);
assign sfp_sda = (sfp_sda_en) ? 1'b0:1'bz;
......@@ -243,66 +243,66 @@ module dut_env
always@(negedge clk_400m_adc)
begin
#625ps;
if(adc_div == 1) begin
adc0_fr <= ~adc0_fr;
adc_div <= 0;
end
else begin
adc_div <= adc_div + 1;
end
#625ps;
if(adc_div == 1) begin
adc0_fr <= ~adc0_fr;
adc_div <= 0;
end
else begin
adc_div <= adc_div + 1;
end
end
always@(posedge adc0_fr)
begin
if ((adc0_data > 400) || (adc0_data < -400)) begin
adc_data_dir = ~adc_data_dir;
end
if (adc_data_dir == 0) begin
adc0_data = adc0_data + 8;
end
else begin
adc0_data = adc0_data - 8;
end
adc0_dat_odd = {4{adc0_data[13]}};
adc0_dat_even = {4{adc0_data[12]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[11]}};
adc0_dat_even = {4{adc0_data[10]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[9]}};
adc0_dat_even = {4{adc0_data[8]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[7]}};
adc0_dat_even = {4{adc0_data[6]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[5]}};
adc0_dat_even = {4{adc0_data[4]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[3]}};
adc0_dat_even = {4{adc0_data[2]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[1]}};
adc0_dat_even = {4{adc0_data[0]}};
#1250ps;
adc0_dat_odd = {4{1'b0}};
adc0_dat_even = {4{1'b0}};
if ((adc0_data > 400) || (adc0_data < -400)) begin
adc_data_dir = ~adc_data_dir;
end
if (adc_data_dir == 0) begin
adc0_data = adc0_data + 8;
end
else begin
adc0_data = adc0_data - 8;
end
adc0_dat_odd = {4{adc0_data[13]}};
adc0_dat_even = {4{adc0_data[12]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[11]}};
adc0_dat_even = {4{adc0_data[10]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[9]}};
adc0_dat_even = {4{adc0_data[8]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[7]}};
adc0_dat_even = {4{adc0_data[6]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[5]}};
adc0_dat_even = {4{adc0_data[4]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[3]}};
adc0_dat_even = {4{adc0_data[2]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[1]}};
adc0_dat_even = {4{adc0_data[0]}};
#1250ps;
adc0_dat_odd = {4{1'b0}};
adc0_dat_even = {4{1'b0}};
end
initial begin
// Skip WR SoftPLL lock
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
endmodule // dut_env
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @ 47a61400
This diff is collapsed.
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
View file @ 47a61400
......@@ -41,8 +41,8 @@ module simple_tdc_driver
);
typedef struct {
int channel;
time ts;
int channel;
time ts;
} acam_fifo_entry;
acam_fifo_entry pulses[$];
......@@ -71,30 +71,30 @@ module simple_tdc_driver
time now;
wait (pulses.size() != 0)
;
;
t = pulses.pop_front();
now = $time;
if (t.ts <= now)
$display("[DUT] <%t> TDC: pulse in the past (%t now=%t)!", $realtime, t.ts, now);
$display("[DUT] <%t> TDC: pulse in the past (%t now=%t)!", $realtime, t.ts, now);
else
begin
const int fifo_n = t.channel / 4;
logic [27:0] val;
begin
const int fifo_n = t.channel / 4;
logic [27:0] val;
#(t.ts - now) ;
#(t.ts - now) ;
val[27:26] = t.channel & 2'b11;
val[25:18] = start;
val[17] = 1'b1;
val[16:0] = (t.ts - start_time) / 81ps;
val[27:26] = t.channel & 2'b11;
val[25:18] = start;
val[17] = 1'b1;
val[16:0] = (t.ts - start_time) / 81ps;
$display("[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)",
$realtime, t.ts, t.channel, start, val[16:0], start_time);
$display("[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)",
$realtime, t.ts, t.channel, start, val[16:0], start_time);
fifos[t.channel / 4].push_back(val);
end
fifos[t.channel / 4].push_back(val);
end
end
initial begin
......@@ -110,34 +110,34 @@ module simple_tdc_driver
always@(posedge clk) begin
start_rep++;
if (start_rep == start_timer) begin
start_rep = 0;
if (restart_pulse) begin
start = 1;
restart_pulse = 0;
start01 = ($time - restart_time) / 81ps;
end
else begin
start_time = $time;
start++;
end
start_rep = 0;
if (restart_pulse) begin
start = 1;
restart_pulse = 0;
start01 = ($time - restart_time) / 81ps;
end
else begin
start_time = $time;
start++;
end
end
end
always@(rd) begin
rdata <= 28'bz;
if (rd == 1'b0) begin
if (addr == 8) begin
rdata <= fifos[0].pop_front();
end
else if (addr == 9) begin
rdata <= fifos[1].pop_front();
end
else if (addr == 10) begin
rdata <= start01;
end
else begin
$display("[DUT] <%t> invalid ACAM read 0x%x", $realtime, addr);
end
if (addr == 8) begin
rdata <= fifos[0].pop_front();
end
else if (addr == 9) begin
rdata <= fifos[1].pop_front();
end
else if (addr == 10) begin
rdata <= start01;
end
else begin
$display("[DUT] <%t> invalid ACAM read 0x%x", $realtime, addr);
end
end
end
......@@ -160,8 +160,8 @@ module simple_fdelay_mon
);
typedef struct {
int channel;
time ts;
int channel;
time ts;
} fifo_entry;
fifo_entry pulses[$];
......@@ -180,28 +180,28 @@ module simple_fdelay_mon
prev = 0;
while (pulses.size() != 0) begin
@pulse ;
now = $time;
$display("[FDEL] <%t> Pulse: len=%x, val=%x, out=%x", now, len, val, pulse);
for(int i = 0; i < 4; i++) begin
if (prev[i] == 1'b0 && pulse[i] == 1'b1) begin
automatic fifo_entry e = pulses.pop_front();
automatic time diff;
$display("[FDEL] pulse on channel %0d", i);
if (e.channel != i) begin
$display("FAIL: [FDEL] Bad channel (expected %0d)", e.channel);
$finish(1);
end
diff = now - e.ts;
if (diff > 2us && diff < -2us) begin
$display("FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t", now, e.ts);
$finish(1);
end
end
end
prev = pulse;
@pulse ;
now = $time;
$display("[FDEL] <%t> Pulse: len=%x, val=%x, out=%x", now, len, val, pulse);
for(int i = 0; i < 4; i++) begin
if (prev[i] == 1'b0 && pulse[i] == 1'b1) begin
automatic fifo_entry e = pulses.pop_front();
automatic time diff;
$display("[FDEL] pulse on channel %0d", i);
if (e.channel != i) begin
$display("FAIL: [FDEL] Bad channel (expected %0d)", e.channel);
$finish(1);
end
diff = now - e.ts;
if (diff > 2us && diff < -2us) begin
$display("FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t", now, e.ts);
$finish(1);
end
end
end
prev = pulse;
end
$display("SUCCESS: done");
$finish(0);
......@@ -213,7 +213,7 @@ module dut_env
(
IVHDWishboneMaster host,
output clk_sys, rst_sys_n,
sfp_txp_o, sfp_txn_o,
sfp_txp_o, sfp_txn_o,
input sfp_rxp_i, sfp_rxn_i
);
......@@ -310,16 +310,16 @@ module dut_env
simple_tdc_driver
TDC
(
.clk(clk_31m5_acam),
.addr(tdc_addr),
.data(tdc_data),
.wr(tdc_wr_n),
.rd(tdc_rd_n),
.ef1(tdc_ef1),
.ef2(tdc_ef2),
.tstart(tdc_start),
.intflag(tdc_int)
);
.clk(clk_31m5_acam),
.addr(tdc_addr),
.data(tdc_data),
.wr(tdc_wr_n),
.rd(tdc_rd_n),
.ef1(tdc_ef1),
.ef2(tdc_ef2),
.tstart(tdc_start),
.intflag(tdc_int)
);
//---------------------------------------------------------------------------
// Fine Delay monitor
......@@ -328,10 +328,10 @@ module dut_env
simple_fdelay_mon
FDL
(
.len (fdl_len),
.val (fdl_val),
.pulse (fdl_pulse)
);
.len (fdl_len),
.val (fdl_val),
.pulse (fdl_pulse)
);
//---------------------------------------------------------------------------
......@@ -341,14 +341,14 @@ module dut_env
gc_sfp_i2c_adapter
SFP_I2C
(
.clk_i (clk_125m_pll),
.rst_n_i (1'b1),
.scl_i (sfp_scl),
.sda_i (sfp_sda),
.sda_en_o (sfp_sda_en),
.sfp_det_valid_i (1'b1),
.sfp_data_i (128'h0123456789ABCDEF0123456789ABCDEF)
);
.clk_i (clk_125m_pll),
.rst_n_i (1'b1),
.scl_i (sfp_scl),
.sda_i (sfp_sda),
.sda_en_o (sfp_sda_en),
.sfp_det_valid_i (1'b1),
.sfp_data_i (128'h0123456789ABCDEF0123456789ABCDEF)
);
assign sfp_sda = (sfp_sda_en) ? 1'b0:1'bz;
......@@ -377,17 +377,17 @@ module dut_env
initial begin
// Skip WR SoftPLL lock
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
endmodule // dut_env
hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
View file @ 47a61400
......@@ -92,9 +92,9 @@ module main;
initial begin
forever begin
if ( ( dev != null ) && ( dev.ready ) )
dev.update ();
#1us;
if ( ( dev != null ) && ( dev.ready ) )
dev.update ();
#1us;
end
end
......
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