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White Rabbit Trigger Distribution
Commits
47a61400
Commit
47a61400
authored
Jun 27, 2019
by
Dimitris Lampridis
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Plain Diff
hdl: cleanup tab characters in simulations
parent
8c8e6bf0
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Showing
8 changed files
with
512 additions
and
512 deletions
+512
-512
wrtd_definitions.svh
hdl/testbench/include/wrtd_definitions.svh
+11
-11
wrtd_driver.svh
hdl/testbench/include/wrtd_driver.svh
+216
-216
wrtd_rep_cap.svh
hdl/testbench/include/wrtd_rep_cap.svh
+27
-27
wrtd_rule.svh
hdl/testbench/include/wrtd_rule.svh
+1
-1
dut_env.sv
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
+55
-55
main.sv
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
+107
-107
dut_env.sv
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
+92
-92
main.sv
hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
+3
-3
No files found.
hdl/testbench/include/wrtd_definitions.svh
View file @
47a61400
...
...
@@ -111,8 +111,8 @@ class WrtdTstamp;
protected
uint32_t
frac
;
function
new
(
uint32_t
seconds
=
0
,
uint32_t
ns
=
0
,
uint32_t
frac
=
0
)
;
uint32_t
ns
=
0
,
uint32_t
frac
=
0
)
;
set
(
seconds
,
ns
,
frac
)
;
endfunction
// new
...
...
@@ -172,12 +172,12 @@ class WrtdId;
function
void
set
(
string
id
)
;
if
(
id
.
len
()
>
`WRTD_ID_LEN
)
$
error
(
"length of string longer than the available storage"
)
;
$
error
(
"length of string longer than the available storage"
)
;
else
begin
this
.
clear
()
;
this
.
id
=
id
;
end
begin
this
.
clear
()
;
this
.
id
=
id
;
end
endfunction
// set
function
string
get
(
)
;
...
...
@@ -189,17 +189,17 @@ class WrtdId;
wrtd_data
d
;
d
=
new
[
`WRTD_ID_LEN
/
4
]
;
for
(
i
=
0
;
i
<
`WRTD_ID_LEN
/
4
;
i
++
)
d
[
i
]
=
0
;
d
[
i
]
=
0
;
for
(
i
=
0
;
i
<
this
.
id
.
len
()
;
i
++
)
d
[
i
/
4
]
|=
this
.
id
[
i
]
<<
(
8
*
(
i
%
4
)
)
;
d
[
i
/
4
]
|=
this
.
id
[
i
]
<<
(
8
*
(
i
%
4
)
)
;
return
d
;
endfunction
// data_pack
function
void
data_unpack
(
wrtd_data
data
)
;
if
(
data
.
size
()
>
`WRTD_ID_LEN
/
4
)
$
error
(
"length of data longer than the available storage"
)
;
$
error
(
"length of data longer than the available storage"
)
;
else
this
.
id
=
{
<<
32
{
{
<<
8
{
data
}
}
}
};
this
.
id
=
{
<<
32
{
{
<<
8
{
data
}
}
}
};
endfunction
// data_unpack
function
int
is_empty
(
)
;
...
...
hdl/testbench/include/wrtd_driver.svh
View file @
47a61400
...
...
@@ -44,8 +44,8 @@ class WrtdDrv;
protected
WrtdRepCapCollection
alarms
;
function
new
(
CBusAccessor
acc
,
uint64_t
base
,
vIMockTurtleIRQ
irq
,
string
name
=
""
,
byte
unsigned
enable_logging
=
1
)
;
vIMockTurtleIRQ
irq
,
string
name
=
""
,
byte
unsigned
enable_logging
=
1
)
;
this
.
name
=
name
;
...
...
@@ -58,9 +58,9 @@ class WrtdDrv;
task
mdisplay
(
string
str
)
;
string
tmp
;
if
(
this
.
name
==
""
)
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
else
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
$
display
(
tmp
)
;
endtask
// mdisplay
...
...
@@ -88,88 +88,88 @@ class WrtdDrv;
this
.
roots
=
new
[
this
.
nbr_cpus
]
;
for
(
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
begin
this
.
hmq_words
[
i
]
=
`TRTL_CONFIG_ROM_MQ_SIZE_PAYLOAD
(
mt
.
rom
.
getHmqDimensions
(
i
,
0
)
)
;
mt
.
enable_hmqi_irq
(
i
,
0
,
1
)
;
mt
.
enable_console_irq
(
i
,
1
)
;
mt
.
reset_core
(
i
,
0
)
;
end
begin
this
.
hmq_words
[
i
]
=
`TRTL_CONFIG_ROM_MQ_SIZE_PAYLOAD
(
mt
.
rom
.
getHmqDimensions
(
i
,
0
)
)
;
mt
.
enable_hmqi_irq
(
i
,
0
,
1
)
;
mt
.
enable_console_irq
(
i
,
1
)
;
mt
.
reset_core
(
i
,
0
)
;
end
fork
begin
for
(
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
begin
// wait for ready notification from firmware
cpu_ready
=
0
;
while
(
cpu_ready
==
0
)
begin
val
=
0
;
if
(
mt
.
pending_cpu_notifications
(
i
)
!=
0
)
begin
mt
.
get_single_cpu_notification
(
i
,
val
)
;
if
(
val
==
TRTL_CPU_NOTIFY_MAIN
)
cpu_ready
=
1
;
end
#
1u
s
;
end
// retrieve address of root
msg_get_config
(
i
,
data
)
;
this
.
roots
[
i
]
.
addr
=
data
[
0
]
;
// retrieve root
msg_readw
(
i
,
this
.
roots
[
i
]
.
addr
,
`WRTD_ROOT_WORD_SIZE
,
data
)
;
begin
for
(
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
begin
// wait for ready notification from firmware
cpu_ready
=
0
;
while
(
cpu_ready
==
0
)
begin
val
=
0
;
if
(
mt
.
pending_cpu_notifications
(
i
)
!=
0
)
begin
mt
.
get_single_cpu_notification
(
i
,
val
)
;
if
(
val
==
TRTL_CPU_NOTIFY_MAIN
)
cpu_ready
=
1
;
end
#
1u
s
;
end
// retrieve address of root
msg_get_config
(
i
,
data
)
;
this
.
roots
[
i
]
.
addr
=
data
[
0
]
;
// retrieve root
msg_readw
(
i
,
this
.
roots
[
i
]
.
addr
,
`WRTD_ROOT_WORD_SIZE
,
data
)
;
this
.
roots
[
i
]
.
fw_name
=
new
()
;
this
.
roots
[
i
]
.
fw_name
.
data_unpack
(
data
[
1
:
4
])
;
this
.
roots
[
i
]
.
fw_id
=
data
[
5
]
;
this
.
roots
[
i
]
.
capabilities
=
(
data
[
6
]
&
'hff000000
)
>>
24
;
this
.
roots
[
i
]
.
nbr_rules
=
(
data
[
6
]
&
'h00ff0000
)
>>
16
;
this
.
roots
[
i
]
.
nbr_alarms
=
(
data
[
6
]
&
'h0000ff00
)
>>
8
;
this
.
roots
[
i
]
.
nbr_devs
=
(
data
[
6
]
&
'h000000ff
)
>>
0
;
for
(
j
=
0
;
j
<
4
;
j
++
)
begin
this
.
roots
[
i
]
.
nbr_channels
[
j
]
=
(
data
[
9
]
>>
j
*
8
)
&
'hff
;
this
.
roots
[
i
]
.
channel_dir
[
j
]
=
(
data
[
10
]
>>
j
*
8
)
&
'hff
;
end
this
.
roots
[
i
]
.
rules_addr
=
data
[
11
]
;
this
.
roots
[
i
]
.
alarms_addr
=
data
[
12
]
;
// init free rule slots
this
.
free_rule_slots
[
i
]
=
this
.
roots
[
i
]
.
nbr_rules
;
// turn on all logging if enabled
if
(
this
.
enable_logging
)
msg_writew
(
i
,
this
.
roots
[
i
]
.
addr
+
32
,
1
,
{
data
[
8
]
|
32'hff
}
)
;
this
.
roots
[
i
]
.
fw_id
=
data
[
5
]
;
this
.
roots
[
i
]
.
capabilities
=
(
data
[
6
]
&
'hff000000
)
>>
24
;
this
.
roots
[
i
]
.
nbr_rules
=
(
data
[
6
]
&
'h00ff0000
)
>>
16
;
this
.
roots
[
i
]
.
nbr_alarms
=
(
data
[
6
]
&
'h0000ff00
)
>>
8
;
this
.
roots
[
i
]
.
nbr_devs
=
(
data
[
6
]
&
'h000000ff
)
>>
0
;
for
(
j
=
0
;
j
<
4
;
j
++
)
begin
this
.
roots
[
i
]
.
nbr_channels
[
j
]
=
(
data
[
9
]
>>
j
*
8
)
&
'hff
;
this
.
roots
[
i
]
.
channel_dir
[
j
]
=
(
data
[
10
]
>>
j
*
8
)
&
'hff
;
end
this
.
roots
[
i
]
.
rules_addr
=
data
[
11
]
;
this
.
roots
[
i
]
.
alarms_addr
=
data
[
12
]
;
// init free rule slots
this
.
free_rule_slots
[
i
]
=
this
.
roots
[
i
]
.
nbr_rules
;
// turn on all logging if enabled
if
(
this
.
enable_logging
)
msg_writew
(
i
,
this
.
roots
[
i
]
.
addr
+
32
,
1
,
{
data
[
8
]
|
32'hff
}
)
;
mdisplay
(
$
sformatf
(
"CPU %0d: WRTD app '%s', id '0x%x'"
,
i
,
this
.
roots
[
i
]
.
fw_name
.
get
()
,
this
.
roots
[
i
]
.
fw_id
)
)
;
end
// initialise rules
this
.
rules
=
new
(
this
.
name
)
;
for
(
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
for
(
j
=
0
;
j
<
this
.
roots
[
i
]
.
nbr_rules
;
j
++
)
begin
new_rule
=
new
(
this
.
name
)
;
this
.
rules
.
collection
.
push_back
(
new_rule
)
;
end
// initialise alarms
this
.
alarms
=
new
(
this
.
name
)
;
for
(
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
for
(
j
=
0
;
j
<
this
.
roots
[
i
]
.
nbr_alarms
;
j
++
)
begin
new_alarm
=
new
(
this
.
name
)
;
this
.
alarms
.
collection
.
push_back
(
new_alarm
)
;
end
end
begin
while
(
i
!=
this
.
nbr_cpus
)
begin
mt
.
update
(
)
;
#
1u
s
;
end
end
end
// initialise rules
this
.
rules
=
new
(
this
.
name
)
;
for
(
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
for
(
j
=
0
;
j
<
this
.
roots
[
i
]
.
nbr_rules
;
j
++
)
begin
new_rule
=
new
(
this
.
name
)
;
this
.
rules
.
collection
.
push_back
(
new_rule
)
;
end
// initialise alarms
this
.
alarms
=
new
(
this
.
name
)
;
for
(
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
for
(
j
=
0
;
j
<
this
.
roots
[
i
]
.
nbr_alarms
;
j
++
)
begin
new_alarm
=
new
(
this
.
name
)
;
this
.
alarms
.
collection
.
push_back
(
new_alarm
)
;
end
end
begin
while
(
i
!=
this
.
nbr_cpus
)
begin
mt
.
update
(
)
;
#
1u
s
;
end
end
join
this
.
ready
=
1
;
...
...
@@ -182,7 +182,7 @@ class WrtdDrv;
MQueueMsg
msg
;
if
(
data
.
size
()
<
`WRTD_CFG_MSG_WORD_SIZE
)
data
=
new
[
`WRTD_CFG_MSG_WORD_SIZE
]
;
data
=
new
[
`WRTD_CFG_MSG_WORD_SIZE
]
;
msg
=
new
(
core
,
0
)
;
msg
.
header
.
flags
=
`TRTL_HMQ_HEADER_FLAG_RPC
|
`TRTL_HMQ_HEADER_FLAG_SYNC
;
...
...
@@ -192,53 +192,53 @@ class WrtdDrv;
while
(
mt
.
hmq_pending_messages
(
msg
.
core
,
0
)
==
0
)
#
1u
s
;
mt
.
hmq_receive_message
(
msg
)
;
if
(
msg
.
header
.
len
!=
`WRTD_CFG_MSG_WORD_SIZE
)
begin
$
error
(
"get_config: unexpected message header length"
)
;
mdisplay
(
$
sformatf
(
"message received: %s"
,
msg
.
tostring
()
)
)
;
end
begin
$
error
(
"get_config: unexpected message header length"
)
;
mdisplay
(
$
sformatf
(
"message received: %s"
,
msg
.
tostring
()
)
)
;
end
for
(
i
=
0
;
i
<
`WRTD_CFG_MSG_WORD_SIZE
;
i
++
)
data
[
i
]
=
msg
.
data
[
i
]
;
data
[
i
]
=
msg
.
data
[
i
]
;
endtask
// msg_get_config
task
msg_readw
(
int
core
,
uint32_t
addr
,
uint32_t
count
,
ref
uint32_t
data
[]
)
;
uint32_t
count
,
ref
uint32_t
data
[]
)
;
int
i
;
MQueueMsg
msg
;
uint32_t
tlen
,
offset
;
if
(
data
.
size
()
<
count
)
data
=
new
[
count
]
;
data
=
new
[
count
]
;
offset
=
0
;
while
(
offset
<
count
)
begin
tlen
=
this
.
hmq_words
[
core
]
-
`WRTD_IO_MSG_WORD_SIZE
;
if
(
tlen
>
count
-
offset
)
tlen
=
count
-
offset
;
msg
=
new
(
core
,
0
)
;
msg
.
header
.
flags
=
`TRTL_HMQ_HEADER_FLAG_RPC
|
`TRTL_HMQ_HEADER_FLAG_SYNC
;
msg
.
header
.
msg_id
=
WRTD_ACTION_READW
;
msg
.
header
.
len
=
`WRTD_IO_MSG_WORD_SIZE
;
msg
.
data
=
'
{
addr
+
offset
,
tlen
};
mt
.
hmq_send_message
(
msg
)
;
while
(
mt
.
hmq_pending_messages
(
msg
.
core
,
0
)
==
0
)
#
1u
s
;
mt
.
hmq_receive_message
(
msg
)
;
if
(
msg
.
header
.
len
!=
tlen
)
begin
$
error
(
"readw: unexpected message header length"
)
;
mdisplay
(
$
sformatf
(
"message received: %s"
,
msg
.
tostring
()
)
)
;
end
for
(
i
=
0
;
i
<
tlen
;
i
++
)
data
[
offset
+
i
]
=
msg
.
data
[
i
]
;
offset
+=
tlen
;
end
begin
tlen
=
this
.
hmq_words
[
core
]
-
`WRTD_IO_MSG_WORD_SIZE
;
if
(
tlen
>
count
-
offset
)
tlen
=
count
-
offset
;
msg
=
new
(
core
,
0
)
;
msg
.
header
.
flags
=
`TRTL_HMQ_HEADER_FLAG_RPC
|
`TRTL_HMQ_HEADER_FLAG_SYNC
;
msg
.
header
.
msg_id
=
WRTD_ACTION_READW
;
msg
.
header
.
len
=
`WRTD_IO_MSG_WORD_SIZE
;
msg
.
data
=
'
{
addr
+
offset
,
tlen
};
mt
.
hmq_send_message
(
msg
)
;
while
(
mt
.
hmq_pending_messages
(
msg
.
core
,
0
)
==
0
)
#
1u
s
;
mt
.
hmq_receive_message
(
msg
)
;
if
(
msg
.
header
.
len
!=
tlen
)
begin
$
error
(
"readw: unexpected message header length"
)
;
mdisplay
(
$
sformatf
(
"message received: %s"
,
msg
.
tostring
()
)
)
;
end
for
(
i
=
0
;
i
<
tlen
;
i
++
)
data
[
offset
+
i
]
=
msg
.
data
[
i
]
;
offset
+=
tlen
;
end
endtask
// msg_readw
task
msg_writew
(
int
core
,
uint32_t
addr
,
uint32_t
count
,
uint32_t
data
[]
)
;
uint32_t
count
,
uint32_t
data
[]
)
;
int
i
;
MQueueMsg
msg
;
uint32_t
tlen
,
offset
;
...
...
@@ -246,22 +246,22 @@ class WrtdDrv;
offset
=
0
;
while
(
offset
<
count
)
begin
tlen
=
this
.
hmq_words
[
core
]
-
`WRTD_IO_MSG_WORD_SIZE
;
if
(
tlen
>
count
-
offset
)
tlen
=
count
-
offset
;
msg
=
new
(
core
,
0
)
;
msg
.
header
.
flags
=
`TRTL_HMQ_HEADER_FLAG_RPC
|
`TRTL_HMQ_HEADER_FLAG_SYNC
;
msg
.
header
.
msg_id
=
WRTD_ACTION_WRITEW
;
msg
.
header
.
len
=
`WRTD_IO_MSG_WORD_SIZE
+
count
;
msg
.
data
=
'
{
addr
+
offset
,
tlen
};
for
(
i
=
0
;
i
<
tlen
;
i
++
)
msg
.
data
[
i
+
2
]
=
data
[
offset
+
i
]
;
mt
.
hmq_send_message
(
msg
)
;
while
(
mt
.
hmq_pending_messages
(
msg
.
core
,
0
)
==
0
)
#
1u
s
;
mt
.
hmq_receive_message
(
msg
)
;
offset
+=
tlen
;
end
begin
tlen
=
this
.
hmq_words
[
core
]
-
`WRTD_IO_MSG_WORD_SIZE
;
if
(
tlen
>
count
-
offset
)
tlen
=
count
-
offset
;
msg
=
new
(
core
,
0
)
;
msg
.
header
.
flags
=
`TRTL_HMQ_HEADER_FLAG_RPC
|
`TRTL_HMQ_HEADER_FLAG_SYNC
;
msg
.
header
.
msg_id
=
WRTD_ACTION_WRITEW
;
msg
.
header
.
len
=
`WRTD_IO_MSG_WORD_SIZE
+
count
;
msg
.
data
=
'
{
addr
+
offset
,
tlen
};
for
(
i
=
0
;
i
<
tlen
;
i
++
)
msg
.
data
[
i
+
2
]
=
data
[
offset
+
i
]
;
mt
.
hmq_send_message
(
msg
)
;
while
(
mt
.
hmq_pending_messages
(
msg
.
core
,
0
)
==
0
)
#
1u
s
;
mt
.
hmq_receive_message
(
msg
)
;
offset
+=
tlen
;
end
endtask
// msg_writew
...
...
@@ -281,8 +281,8 @@ class WrtdDrv;
endtask
// remove_rule
task
set_rule
(
string
rep_cap_id
,
string
src
,
string
dst
,
uint32_t
delay_ns
)
;
string
src
,
string
dst
,
uint32_t
delay_ns
)
;
int
idx
;
WrtdRule
rule
;
...
...
@@ -290,10 +290,10 @@ class WrtdDrv;
idx
=
this
.
rules
.
find
(
rep_cap_id
)
;
if
(
idx
==
-
1
)
$
error
(
"%s repeated capability ID cannot be set because it does not exist"
,
rep_cap_id
)
;
$
error
(
"%s repeated capability ID cannot be set because it does not exist"
,
rep_cap_id
)
;
if
(
this
.
rules
.
collection
[
idx
]
.
is_enabled
(
)
)
$
error
(
"%s repeated capability ID cannot be set because it is enabled"
,
rep_cap_id
)
;
$
error
(
"%s repeated capability ID cannot be set because it is enabled"
,
rep_cap_id
)
;
$
cast
(
rule
,
this
.
rules
.
collection
[
idx
]
)
;
...
...
@@ -310,7 +310,7 @@ class WrtdDrv;
WrtdRule
rule
;
if
(
idx
<
0
)
$
error
(
"cannot write rule with negative index"
)
;
$
error
(
"cannot write rule with negative index"
)
;
$
cast
(
rule
,
this
.
rules
.
collection
[
idx
]
)
;
...
...
@@ -322,7 +322,7 @@ class WrtdDrv;
endtask
// write_rule
function
void
map_local_channel_to_cpu
(
string
ch_id
,
int
ch_dir
,
ref
int
core
,
ref
int
ch_idx
)
;
ref
int
core
,
ref
int
ch_idx
)
;
int
i
,
j
,
k
,
idx_in
,
idx_out
,
dev_dir
;
string
dev_id
;
...
...
@@ -334,23 +334,23 @@ class WrtdDrv;
ch_idx
=
-
1
;
for
(
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
for
(
j
=
0
;
j
<
this
.
roots
[
i
]
.
nbr_devs
;
j
++
)
begin
dev_dir
=
this
.
roots
[
i
]
.
channel_dir
[
j
]
;
for
(
k
=
0
;
k
<
this
.
roots
[
i
]
.
nbr_channels
[
j
]
;
k
++
)
begin
if
(
dev_dir
==
WRTD_DIR_INPUT
)
dev_id
=
$
sformatf
(
"LC-I%0d"
,
idx_in
++
)
;
else
dev_id
=
$
sformatf
(
"LC-O%0d"
,
idx_out
++
)
;
if
(
(
dev_dir
==
ch_dir
)
&&
(
dev_id
==
ch_id
)
)
begin
core
=
i
;
ch_idx
=
k
;
return
;
end
end
end
for
(
j
=
0
;
j
<
this
.
roots
[
i
]
.
nbr_devs
;
j
++
)
begin
dev_dir
=
this
.
roots
[
i
]
.
channel_dir
[
j
]
;
for
(
k
=
0
;
k
<
this
.
roots
[
i
]
.
nbr_channels
[
j
]
;
k
++
)
begin
if
(
dev_dir
==
WRTD_DIR_INPUT
)
dev_id
=
$
sformatf
(
"LC-I%0d"
,
idx_in
++
)
;
else
dev_id
=
$
sformatf
(
"LC-O%0d"
,
idx_out
++
)
;
if
(
(
dev_dir
==
ch_dir
)
&&
(
dev_id
==
ch_id
)
)
begin
core
=
i
;
ch_idx
=
k
;
return
;
end
end
end
endfunction
// map_local_channel_to_cpu
...
...
@@ -364,7 +364,7 @@ class WrtdDrv;
idx
=
this
.
rules
.
find
(
rep_cap_id
)
;
if
(
idx
==
-
1
)
$
error
(
"%s repeated capability ID cannot be enabled because it does not exist"
,
rep_cap_id
)
;
$
error
(
"%s repeated capability ID cannot be enabled because it does not exist"
,
rep_cap_id
)
;
$
cast
(
rule
,
this
.
rules
.
collection
[
idx
]
)
;
...
...
@@ -378,42 +378,42 @@ class WrtdDrv;
map_local_channel_to_cpu
(
rule
.
get_dst
()
,
WRTD_DIR_OUTPUT
,
dst_cpu
,
dst_ch
)
;
if
(
dst_cpu
>=
0
)
// local output device
begin
/* If source is network message and this cpu can receive from
network, set cpu affinity to this cpu */
if
(
(
src_cpu
==
-
1
)
&&
(
this
.
roots
[
dst_cpu
]
.
capabilities
&
`WRTD_CAP_NET_RX
)
)
src_cpu
=
dst_cpu
;
/* Otherwise find the first cpu that is capable of net RX */
else
for
(
src_cpu
=
0
;
src_cpu
<
this
.
nbr_cpus
;
src_cpu
++
)
if
(
this
.
roots
[
src_cpu
]
.
capabilities
&
`WRTD_CAP_NET_RX
)
break
;
end
begin
/* If source is network message and this cpu can receive from
network, set cpu affinity to this cpu */
if
(
(
src_cpu
==
-
1
)
&&
(
this
.
roots
[
dst_cpu
]
.
capabilities
&
`WRTD_CAP_NET_RX
)
)
src_cpu
=
dst_cpu
;
/* Otherwise find the first cpu that is capable of net RX */
else
for
(
src_cpu
=
0
;
src_cpu
<
this
.
nbr_cpus
;
src_cpu
++
)
if
(
this
.
roots
[
src_cpu
]
.
capabilities
&
`WRTD_CAP_NET_RX
)
break
;
end
else
// network destination
begin
dst_ch
=
`WRTD_DEST_CH_NET
;
/* If source cpu can also send to
network, set dest cpu affinity to that cpu */
if
(
(
src_cpu
>=
0
)
&&
(
this
.
roots
[
src_cpu
]
.
capabilities
&
`WRTD_CAP_NET_TX
)
)
dst_cpu
=
src_cpu
;
/* Otherwise find the first cpu that is capable of net TX */
else
for
(
dst_cpu
=
0
;
dst_cpu
<
this
.
nbr_cpus
;
dst_cpu
++
)
if
(
this
.
roots
[
dst_cpu
]
.
capabilities
&
`WRTD_CAP_NET_TX
)
break
;
end
begin
dst_ch
=
`WRTD_DEST_CH_NET
;
/* If source cpu can also send to
network, set dest cpu affinity to that cpu */
if
(
(
src_cpu
>=
0
)
&&
(
this
.
roots
[
src_cpu
]
.
capabilities
&
`WRTD_CAP_NET_TX
)
)
dst_cpu
=
src_cpu
;
/* Otherwise find the first cpu that is capable of net TX */
else
for
(
dst_cpu
=
0
;
dst_cpu
<
this
.
nbr_cpus
;
dst_cpu
++
)
if
(
this
.
roots
[
dst_cpu
]
.
capabilities
&
`WRTD_CAP_NET_TX
)
break
;
end
// TODO: handle network to network events
if
(
(
src_cpu
<
0
)
||
(
dst_cpu
<
0
)
||
(
src_cpu
>=
this
.
nbr_cpus
)
||
(
dst_cpu
>=
this
.
nbr_cpus
)
)
$
error
(
"cannot determine source and/or destination cpu for rule"
)
;
(
src_cpu
>=
this
.
nbr_cpus
)
||
(
dst_cpu
>=
this
.
nbr_cpus
)
)
$
error
(
"cannot determine source and/or destination cpu for rule"
)
;
/* If the same CPU can handle both input and output, use special value so that
the firmware will know not to forward this event to another CPU (it does not
know its own index) */
the firmware will know not to forward this event to another CPU (it does not
know its own index) */
if
(
src_cpu
==
dst_cpu
)
dst_cpu
=
`WRTD_DEST_CPU_LOCAL
;
dst_cpu
=
`WRTD_DEST_CPU_LOCAL
;
// TODO: handle free_rule_slots per cpu
...
...
@@ -449,7 +449,7 @@ class WrtdDrv;
uint32_t
data
[]
;
if
(
idx
<
0
)
$
error
(
"cannot write alarm with negative index"
)
;
$
error
(
"cannot write alarm with negative index"
)
;
core
=
this
.
alarms
.
collection
[
idx
]
.
get_core
(
)
;
//index = this.alarms.collection[idx].get_index ();
...
...
@@ -474,10 +474,10 @@ class WrtdDrv;
ret
=
""
;
if
(
msg
.
header
.
msg_id
!=
`WRTD_ACTION_LOG
)
begin
$
error
(
"log_msg_tostring: unknown message id %.8x"
,
msg
.
header
.
msg_id
)
;
return
ret
;
end
begin
$
error
(
"log_msg_tostring: unknown message id %.8x"
,
msg
.
header
.
msg_id
)
;
return
ret
;
end
msg_tstamp
=
new
()
;
msg_tstamp
.
data_unpack
(
msg
.
data
[
11
:
13
]
)
;
...
...
@@ -497,29 +497,29 @@ class WrtdDrv;
case
(
msg_type
)
WRTD_LOG_MSG_EV_GENERATED
:
begin
$
cast
(
gen_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
gen_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_CONSUMED
:
begin
$
cast
(
con_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
con_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_DISCARDED
:
begin
$
cast
(
dsc_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
dsc_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_NETWORK
:
begin
$
cast
(
net_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
net_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_GENERATED
:
begin
$
cast
(
gen_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
gen_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_CONSUMED
:
begin
$
cast
(
con_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
con_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_DISCARDED
:
begin
$
cast
(
dsc_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
dsc_reason
.
name
()
)
};
end
WRTD_LOG_MSG_EV_NETWORK
:
begin
$
cast
(
net_reason
,
msg
.
data
[
1
]
)
;
ret
=
{
ret
,
$
sformatf
(
", reason: %s"
,
net_reason
.
name
()
)
};
end
endcase
;
// case ( msg_type )
...
...
@@ -532,22 +532,22 @@ class WrtdDrv;
MQueueMsg
msg
;
for
(
int
i
=
0
;
i
<
this
.
nbr_cpus
;
i
++
)
begin
while
(
mt
.
hmq_pending_messages
(
i
,
0
)
)
begin
msg
=
new
(
i
,
0
)
;
mt
.
hmq_peek_message
(
msg
)
;
if
(
msg
.
header
.
msg_id
!=
`WRTD_ACTION_LOG
)
break
;
mt
.
hmq_receive_message
(
msg
)
;
mdisplay
(
$
sformatf
(
"LOG MSG from core %0d: %s"
,
i
,
log_msg_tostring
(
msg
)
)
)
;
end
end
begin
while
(
mt
.
hmq_pending_messages
(
i
,
0
)
)
begin
msg
=
new
(
i
,
0
)
;
mt
.
hmq_peek_message
(
msg
)
;
if
(
msg
.
header
.
msg_id
!=
`WRTD_ACTION_LOG
)
break
;
mt
.
hmq_receive_message
(
msg
)
;
mdisplay
(
$
sformatf
(
"LOG MSG from core %0d: %s"
,
i
,
log_msg_tostring
(
msg
)
)
)
;
end
end
endtask
// check_logs
task
update
(
)
;
mt
.
update
(
)
;
if
(
this
.
enable_logging
)
check_logs
(
)
;
check_logs
(
)
;
endtask
// update
endclass
// WrtdDrv
...
...
hdl/testbench/include/wrtd_rep_cap.svh
View file @
47a61400
...
...
@@ -47,9 +47,9 @@ virtual class WrtdRepCap;
task
mdisplay
(
string
str
)
;
string
tmp
;
if
(
this
.
name
==
""
)
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
else
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
$
display
(
tmp
)
;
endtask
// mdisplay
...
...
@@ -83,9 +83,9 @@ virtual class WrtdRepCap;
function
void
set_enable
(
int
enable
)
;
if
(
enable
>
0
)
this
.
enabled
=
1
;
this
.
enabled
=
1
;
else
this
.
enabled
=
0
;
this
.
enabled
=
0
;
endfunction
// set_enable
function
void
set_disable
(
)
;
...
...
@@ -110,17 +110,17 @@ class WrtdRepCapCollection;
task
mdisplay
(
string
str
)
;
string
tmp
;
if
(
this
.
name
==
""
)
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
else
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
$
display
(
tmp
)
;
endtask
// mdisplay
function
void
validate_id
(
string
rep_cap_id
)
;
if
(
rep_cap_id
.
len
()
>
`WRTD_ID_LEN
)
$
error
(
"repeated capability name '%s' is too long"
,
rep_cap_id
)
;
$
error
(
"repeated capability name '%s' is too long"
,
rep_cap_id
)
;
if
(
rep_cap_id
.
len
()
==
0
)
$
error
(
"repeated capability name is null"
)
;
$
error
(
"repeated capability name is null"
)
;
endfunction
// validate_id
function
int
add
(
string
rep_cap_id
)
;
...
...
@@ -131,21 +131,21 @@ class WrtdRepCapCollection;
idx
=
-
1
;
for
(
i
=
0
;
i
<
this
.
collection
.
size
()
;
i
++
)
begin
begin
if
(
this
.
collection
[
i
]
.
match
(
rep_cap_id
)
)
begin
$
error
(
"'%s' repeated capability ID already exists"
,
rep_cap_id
)
;
return
-
1
;
end
if
(
idx
==
-
1
&&
this
.
collection
[
i
]
.
is_free
()
)
idx
=
i
;
end
if
(
this
.
collection
[
i
]
.
match
(
rep_cap_id
)
)
begin
$
error
(
"'%s' repeated capability ID already exists"
,
rep_cap_id
)
;
return
-
1
;
end
if
(
idx
==
-
1
&&
this
.
collection
[
i
]
.
is_free
()
)
idx
=
i
;
end
if
(
idx
==
-
1
)
$
error
(
"cannot add '%s' repeated capability, no space available"
,
rep_cap_id
)
;
$
error
(
"cannot add '%s' repeated capability, no space available"
,
rep_cap_id
)
;
else
this
.
collection
[
idx
]
.
set_rep_cap_id
(
rep_cap_id
)
;
this
.
collection
[
idx
]
.
set_rep_cap_id
(
rep_cap_id
)
;
return
idx
;
endfunction
// add
...
...
@@ -156,8 +156,8 @@ class WrtdRepCapCollection;
validate_id
(
rep_cap_id
)
;
for
(
i
=
0
;
i
<
this
.
collection
.
size
()
;
i
++
)
if
(
this
.
collection
[
i
]
.
match
(
rep_cap_id
)
)
return
i
;
if
(
this
.
collection
[
i
]
.
match
(
rep_cap_id
)
)
return
i
;
return
-
1
;
endfunction
// find
...
...
@@ -168,15 +168,15 @@ class WrtdRepCapCollection;
idx
=
find
(
rep_cap_id
)
;
if
(
idx
==
-
1
)
begin
$
error
(
"%s repeated capability ID cannot be removed because it does not exist"
,
rep_cap_id
)
;
return
idx
;
end
begin
$
error
(
"%s repeated capability ID cannot be removed because it does not exist"
,
rep_cap_id
)
;
return
idx
;
end
if
(
this
.
collection
[
idx
]
.
is_enabled
(
)
)
$
error
(
"%s repeated capability ID cannot be removed because it is enabled"
,
rep_cap_id
)
;
$
error
(
"%s repeated capability ID cannot be removed because it is enabled"
,
rep_cap_id
)
;
else
this
.
collection
[
idx
]
.
clear
()
;
this
.
collection
[
idx
]
.
clear
()
;
return
idx
;
endfunction
// remove
...
...
hdl/testbench/include/wrtd_rule.svh
View file @
47a61400
...
...
@@ -38,7 +38,7 @@ class WrtdRule extends WrtdRepCap;
protected
uint32_t
hold_off_ns
;
protected
uint32_t
resync_period_ns
;
protected
uint32_t
resync_factor
;
int
hash_chain
;
int
hash_chain
;
protected
uint32_t
rx_events
;
protected
WrtdTstamp
rx_last
;
protected
uint32_t
tx_events
;
...
...
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @
47a61400
...
...
@@ -226,14 +226,14 @@ module dut_env
gc_sfp_i2c_adapter
SFP_I2C
(
.
clk_i
(
clk_125m_pll
)
,
.
rst_n_i
(
1'b1
)
,
.
scl_i
(
sfp_scl
)
,
.
sda_i
(
sfp_sda
)
,
.
sda_en_o
(
sfp_sda_en
)
,
.
sfp_det_valid_i
(
1'b1
)
,
.
sfp_data_i
(
128'h0123456789ABCDEF0123456789ABCDEF
)
)
;
.
clk_i
(
clk_125m_pll
)
,
.
rst_n_i
(
1'b1
)
,
.
scl_i
(
sfp_scl
)
,
.
sda_i
(
sfp_sda
)
,
.
sda_en_o
(
sfp_sda_en
)
,
.
sfp_det_valid_i
(
1'b1
)
,
.
sfp_data_i
(
128'h0123456789ABCDEF0123456789ABCDEF
)
)
;
assign
sfp_sda
=
(
sfp_sda_en
)
?
1'b0
:
1'bz
;
...
...
@@ -243,66 +243,66 @@ module dut_env
always
@
(
negedge
clk_400m_adc
)
begin
#
625
ps
;
if
(
adc_div
==
1
)
begin
adc0_fr
<=
~
adc0_fr
;
adc_div
<=
0
;
end
else
begin
adc_div
<=
adc_div
+
1
;
end
#
625
ps
;
if
(
adc_div
==
1
)
begin
adc0_fr
<=
~
adc0_fr
;
adc_div
<=
0
;
end
else
begin
adc_div
<=
adc_div
+
1
;
end
end
always
@
(
posedge
adc0_fr
)
begin
if
((
adc0_data
>
400
)
||
(
adc0_data
<
-
400
))
begin
adc_data_dir
=
~
adc_data_dir
;
end
if
(
adc_data_dir
==
0
)
begin
adc0_data
=
adc0_data
+
8
;
end
else
begin
adc0_data
=
adc0_data
-
8
;
end
adc0_dat_odd
=
{
4
{
adc0_data
[
13
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
12
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
11
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
10
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
9
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
8
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
7
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
6
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
5
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
4
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
3
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
2
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
1
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
0
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
1'b0
}};
adc0_dat_even
=
{
4
{
1'b0
}};
if
((
adc0_data
>
400
)
||
(
adc0_data
<
-
400
))
begin
adc_data_dir
=
~
adc_data_dir
;
end
if
(
adc_data_dir
==
0
)
begin
adc0_data
=
adc0_data
+
8
;
end
else
begin
adc0_data
=
adc0_data
-
8
;
end
adc0_dat_odd
=
{
4
{
adc0_data
[
13
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
12
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
11
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
10
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
9
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
8
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
7
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
6
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
5
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
4
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
3
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
2
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
1
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
0
]
}};
#
1250
ps
;
adc0_dat_odd
=
{
4
{
1'b0
}};
adc0_dat_even
=
{
4
{
1'b0
}};
end
initial
begin
// Skip WR SoftPLL lock
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D1
.
OPMODE_dly
=
0
;
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D1
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D2
.
OPMODE_dly
=
0
;
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D2
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
end
// initial begin
endmodule
// dut_env
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @
47a61400
...
...
@@ -63,74 +63,74 @@ module main;
wait
((
hostA
.
ready
==
1'b1
)
&&
(
hostB
.
ready
==
1'b1
))
;
fork
begin
accA
=
hostA
.
get_accessor
()
;
accA
.
set_default_xfer_size
(
4
)
;
devA
=
new
(
accA
,
MT_BASE
,
MtIrqMonitorA
,
"DUT:A"
)
;
devA
.
init
()
;
devA
.
add_rule
(
"rule0"
)
;
devA
.
set_rule
(
"rule0"
,
"LC-I5"
,
"NET0"
,
0
)
;
devA
.
enable_rule
(
"rule0"
)
;
// Config DUTA to trigger on external trigger and get 64 samples
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h40
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h01
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_SAT
,
'h7fff
)
;
val
=
(
1'b1
<<
`FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET
)
;
val
|=
(
1'b1
<<
`FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT_OFFSET
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_EN
,
val
)
;
expected
=
'h39
;
accA
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_STA
,
val
)
;
if
(
val
!=
expected
)
$
fatal
(
1
,
"ADC status error (got 0x%8x, expected 0x%8x)."
,
val
,
expected
)
;
$
display
(
"[DUT:A] <%t> ADC configured and armed"
,
$
realtime
)
;
wait
(
duta_acq_state
==
1
)
;
end
begin
accB
=
hostB
.
get_accessor
()
;
accB
.
set_default_xfer_size
(
4
)
;
devB
=
new
(
accB
,
MT_BASE
,
MtIrqMonitorB
,
"DUT:B"
)
;
devB
.
init
()
;
devB
.
add_rule
(
"rule0"
)
;
devB
.
set_rule
(
"rule0"
,
"NET0"
,
"LC-O1"
,
50000
)
;
devB
.
enable_rule
(
"rule0"
)
;
// Config DUTB to trigger on WRTD and get 64 samples
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h40
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h01
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_SAT
,
'h7fff
)
;
val
=
(
1'b1
<<
`FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_EN
,
val
)
;
expected
=
'h39
;
accB
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_STA
,
val
)
;
if
(
val
!=
expected
)
$
fatal
(
1
,
"ADC status error (got 0x%8x, expected 0x%8x)."
,
val
,
expected
)
;
$
display
(
"[DUT:B] <%t> ADC configured and armed"
,
$
realtime
)
;
wait
(
dutb_acq_state
==
1
)
;
end
begin
accA
=
hostA
.
get_accessor
()
;
accA
.
set_default_xfer_size
(
4
)
;
devA
=
new
(
accA
,
MT_BASE
,
MtIrqMonitorA
,
"DUT:A"
)
;
devA
.
init
()
;
devA
.
add_rule
(
"rule0"
)
;
devA
.
set_rule
(
"rule0"
,
"LC-I5"
,
"NET0"
,
0
)
;
devA
.
enable_rule
(
"rule0"
)
;
// Config DUTA to trigger on external trigger and get 64 samples
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h40
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h01
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_GAIN
,
'h8000
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h7fff
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_SAT
,
'h7fff
)
;
val
=
(
1'b1
<<
`FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET
)
;
val
|=
(
1'b1
<<
`FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT_OFFSET
)
;
accA
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_EN
,
val
)
;
expected
=
'h39
;
accA
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_STA
,
val
)
;
if
(
val
!=
expected
)
$
fatal
(
1
,
"ADC status error (got 0x%8x, expected 0x%8x)."
,
val
,
expected
)
;
$
display
(
"[DUT:A] <%t> ADC configured and armed"
,
$
realtime
)
;
wait
(
duta_acq_state
==
1
)
;
end
begin
accB
=
hostB
.
get_accessor
()
;
accB
.
set_default_xfer_size
(
4
)
;
devB
=
new
(
accB
,
MT_BASE
,
MtIrqMonitorB
,
"DUT:B"
)
;
devB
.
init
()
;
devB
.
add_rule
(
"rule0"
)
;
devB
.
set_rule
(
"rule0"
,
"NET0"
,
"LC-O1"
,
50000
)
;
devB
.
enable_rule
(
"rule0"
)
;
// Config DUTB to trigger on WRTD and get 64 samples
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES
,
'h00
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES
,
'h40
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_SHOTS
,
'h01
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_GAIN
,
'h8000
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH1_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH2_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH3_SAT
,
'h7fff
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_CH4_SAT
,
'h7fff
)
;
val
=
(
1'b1
<<
`FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET
)
;
accB
.
write
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_EN
,
val
)
;
expected
=
'h39
;
accB
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_STA
,
val
)
;
if
(
val
!=
expected
)
$
fatal
(
1
,
"ADC status error (got 0x%8x, expected 0x%8x)."
,
val
,
expected
)
;
$
display
(
"[DUT:B] <%t> ADC configured and armed"
,
$
realtime
)
;
wait
(
dutb_acq_state
==
1
)
;
end
join
#
50u
s
;
...
...
@@ -146,57 +146,57 @@ module main;
duta_ext_trig
<=
1'b0
;
fork
begin
wait
(
duta_acq_state
==
1
)
;
$
display
(
"[DUT:A] <%t> END ACQ 1"
,
$
realtime
)
;
begin
wait
(
duta_acq_state
==
1
)
;
$
display
(
"[DUT:A] <%t> END ACQ 1"
,
$
realtime
)
;
accA
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_POS
,
val
)
;
$
display
(
"[DUT:A] <%t> TRIG POSITION %.8x"
,
$
realtime
,
val
)
;
accA
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_POS
,
val
)
;
$
display
(
"[DUT:A] <%t> TRIG POSITION %.8x"
,
$
realtime
,
val
)
;
// DMA transfer
accA
.
write
(
'h2008
,
val
)
;
// dma start addr
// DMA transfer
accA
.
write
(
'h2008
,
val
)
;
// dma start addr
accA
.
write
(
'h200C
,
'h00001000
)
;
// host addr
accA
.
write
(
'h2010
,
'h00000000
)
;
accA
.
write
(
'h200C
,
'h00001000
)
;
// host addr
accA
.
write
(
'h2010
,
'h00000000
)
;
accA
.
write
(
'h2014
,
'h00000100
)
;
// len << 2
accA
.
write
(
'h2014
,
'h00000100
)
;
// len << 2
accA
.
write
(
'h2018
,
'h00000000
)
;
// next
accA
.
write
(
'h201C
,
'h00000000
)
;
accA
.
write
(
'h2018
,
'h00000000
)
;
// next
accA
.
write
(
'h201C
,
'h00000000
)
;
accA
.
write
(
'h2020
,
'h00000000
)
;
// attrib: pcie -> host
accA
.
write
(
'h2020
,
'h00000000
)
;
// attrib: pcie -> host
accA
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
accA
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
wait
(
DUTA
.
DUT
.
dma_irq
[
0
]
==
1
)
;
$
display
(
"[DUT:A] <%t> END DMA 1"
,
$
realtime
)
;
end
wait
(
DUTA
.
DUT
.
dma_irq
[
0
]
==
1
)
;
$
display
(
"[DUT:A] <%t> END DMA 1"
,
$
realtime
)
;
end
begin
wait
(
dutb_acq_state
==
1
)
;
$
display
(
"[DUT:B] <%t> END ACQ 1"
,
$
realtime
)
;
begin
wait
(
dutb_acq_state
==
1
)
;
$
display
(
"[DUT:B] <%t> END ACQ 1"
,
$
realtime
)
;
accB
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_POS
,
val
)
;
$
display
(
"[DUT:B] <%t> TRIG POSITION %.8x"
,
$
realtime
,
val
)
;
accB
.
read
(
`ADC_CSR_BASE
+
`ADDR_FMC_ADC_100MS_CSR_TRIG_POS
,
val
)
;
$
display
(
"[DUT:B] <%t> TRIG POSITION %.8x"
,
$
realtime
,
val
)
;
// DMA transfer
accB
.
write
(
'h2008
,
val
)
;
// dma start addr
// DMA transfer
accB
.
write
(
'h2008
,
val
)
;
// dma start addr
accB
.
write
(
'h200C
,
'h00001000
)
;
// host addr
accB
.
write
(
'h2010
,
'h00000000
)
;
accB
.
write
(
'h200C
,
'h00001000
)
;
// host addr
accB
.
write
(
'h2010
,
'h00000000
)
;
accB
.
write
(
'h2014
,
'h00000100
)
;
// len << 2
accB
.
write
(
'h2014
,
'h00000100
)
;
// len << 2
accB
.
write
(
'h2018
,
'h00000000
)
;
// next
accB
.
write
(
'h201C
,
'h00000000
)
;
accB
.
write
(
'h2018
,
'h00000000
)
;
// next
accB
.
write
(
'h201C
,
'h00000000
)
;
accB
.
write
(
'h2020
,
'h00000000
)
;
// attrib: pcie -> host
accB
.
write
(
'h2020
,
'h00000000
)
;
// attrib: pcie -> host
accB
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
accB
.
write
(
'h2000
,
'h00000001
)
;
// xfer start
wait
(
DUTB
.
DUT
.
dma_irq
[
0
]
==
1
)
;
$
display
(
"[DUT:B] <%t> END DMA 1"
,
$
realtime
)
;
end
wait
(
DUTB
.
DUT
.
dma_irq
[
0
]
==
1
)
;
$
display
(
"[DUT:B] <%t> END DMA 1"
,
$
realtime
)
;
end
join
...
...
@@ -205,11 +205,11 @@ module main;
initial
begin
forever
begin
if
(
(
devA
!=
null
)
&&
(
devA
.
ready
)
)
devA
.
update
()
;
if
(
(
devB
!=
null
)
&&
(
devB
.
ready
)
)
devB
.
update
()
;
#
1u
s
;
if
(
(
devA
!=
null
)
&&
(
devA
.
ready
)
)
devA
.
update
()
;
if
(
(
devB
!=
null
)
&&
(
devB
.
ready
)
)
devB
.
update
()
;
#
1u
s
;
end
end
...
...
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
View file @
47a61400
...
...
@@ -41,8 +41,8 @@ module simple_tdc_driver
)
;
typedef
struct
{
int
channel
;
time
ts
;
int
channel
;
time
ts
;
}
acam_fifo_entry
;
acam_fifo_entry
pulses
[$]
;
...
...
@@ -71,30 +71,30 @@ module simple_tdc_driver
time
now
;
wait
(
pulses
.
size
()
!=
0
)
;
;
t
=
pulses
.
pop_front
()
;
now
=
$
time
;
if
(
t
.
ts
<=
now
)
$
display
(
"[DUT] <%t> TDC: pulse in the past (%t now=%t)!"
,
$
realtime
,
t
.
ts
,
now
)
;
$
display
(
"[DUT] <%t> TDC: pulse in the past (%t now=%t)!"
,
$
realtime
,
t
.
ts
,
now
)
;
else
begin
const
int
fifo_n
=
t
.
channel
/
4
;
logic
[
27
:
0
]
val
;
begin
const
int
fifo_n
=
t
.
channel
/
4
;
logic
[
27
:
0
]
val
;
#(
t
.
ts
-
now
)
;
#(
t
.
ts
-
now
)
;
val
[
27
:
26
]
=
t
.
channel
&
2'b11
;
val
[
25
:
18
]
=
start
;
val
[
17
]
=
1'b1
;
val
[
16
:
0
]
=
(
t
.
ts
-
start_time
)
/
81
ps
;
val
[
27
:
26
]
=
t
.
channel
&
2'b11
;
val
[
25
:
18
]
=
start
;
val
[
17
]
=
1'b1
;
val
[
16
:
0
]
=
(
t
.
ts
-
start_time
)
/
81
ps
;
$
display
(
"[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)"
,
$
realtime
,
t
.
ts
,
t
.
channel
,
start
,
val
[
16
:
0
]
,
start_time
)
;
$
display
(
"[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)"
,
$
realtime
,
t
.
ts
,
t
.
channel
,
start
,
val
[
16
:
0
]
,
start_time
)
;
fifos
[
t
.
channel
/
4
]
.
push_back
(
val
)
;
end
fifos
[
t
.
channel
/
4
]
.
push_back
(
val
)
;
end
end
initial
begin
...
...
@@ -110,34 +110,34 @@ module simple_tdc_driver
always
@
(
posedge
clk
)
begin
start_rep
++;
if
(
start_rep
==
start_timer
)
begin
start_rep
=
0
;
if
(
restart_pulse
)
begin
start
=
1
;
restart_pulse
=
0
;
start01
=
($
time
-
restart_time
)
/
81
ps
;
end
else
begin
start_time
=
$
time
;
start
++;
end
start_rep
=
0
;
if
(
restart_pulse
)
begin
start
=
1
;
restart_pulse
=
0
;
start01
=
($
time
-
restart_time
)
/
81
ps
;
end
else
begin
start_time
=
$
time
;
start
++;
end
end
end
always
@
(
rd
)
begin
rdata
<=
28'bz
;
if
(
rd
==
1'b0
)
begin
if
(
addr
==
8
)
begin
rdata
<=
fifos
[
0
]
.
pop_front
()
;
end
else
if
(
addr
==
9
)
begin
rdata
<=
fifos
[
1
]
.
pop_front
()
;
end
else
if
(
addr
==
10
)
begin
rdata
<=
start01
;
end
else
begin
$
display
(
"[DUT] <%t> invalid ACAM read 0x%x"
,
$
realtime
,
addr
)
;
end
if
(
addr
==
8
)
begin
rdata
<=
fifos
[
0
]
.
pop_front
()
;
end
else
if
(
addr
==
9
)
begin
rdata
<=
fifos
[
1
]
.
pop_front
()
;
end
else
if
(
addr
==
10
)
begin
rdata
<=
start01
;
end
else
begin
$
display
(
"[DUT] <%t> invalid ACAM read 0x%x"
,
$
realtime
,
addr
)
;
end
end
end
...
...
@@ -160,8 +160,8 @@ module simple_fdelay_mon
)
;
typedef
struct
{
int
channel
;
time
ts
;
int
channel
;
time
ts
;
}
fifo_entry
;
fifo_entry
pulses
[$]
;
...
...
@@ -180,28 +180,28 @@ module simple_fdelay_mon
prev
=
0
;
while
(
pulses
.
size
()
!=
0
)
begin
@
pulse
;
now
=
$
time
;
$
display
(
"[FDEL] <%t> Pulse: len=%x, val=%x, out=%x"
,
now
,
len
,
val
,
pulse
)
;
for
(
int
i
=
0
;
i
<
4
;
i
++
)
begin
if
(
prev
[
i
]
==
1'b0
&&
pulse
[
i
]
==
1'b1
)
begin
automatic
fifo_entry
e
=
pulses
.
pop_front
()
;
automatic
time
diff
;
$
display
(
"[FDEL] pulse on channel %0d"
,
i
)
;
if
(
e
.
channel
!=
i
)
begin
$
display
(
"FAIL: [FDEL] Bad channel (expected %0d)"
,
e
.
channel
)
;
$
finish
(
1
)
;
end
diff
=
now
-
e
.
ts
;
if
(
diff
>
2u
s
&&
diff
<
-
2u
s
)
begin
$
display
(
"FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t"
,
now
,
e
.
ts
)
;
$
finish
(
1
)
;
end
end
end
prev
=
pulse
;
@
pulse
;
now
=
$
time
;
$
display
(
"[FDEL] <%t> Pulse: len=%x, val=%x, out=%x"
,
now
,
len
,
val
,
pulse
)
;
for
(
int
i
=
0
;
i
<
4
;
i
++
)
begin
if
(
prev
[
i
]
==
1'b0
&&
pulse
[
i
]
==
1'b1
)
begin
automatic
fifo_entry
e
=
pulses
.
pop_front
()
;
automatic
time
diff
;
$
display
(
"[FDEL] pulse on channel %0d"
,
i
)
;
if
(
e
.
channel
!=
i
)
begin
$
display
(
"FAIL: [FDEL] Bad channel (expected %0d)"
,
e
.
channel
)
;
$
finish
(
1
)
;
end
diff
=
now
-
e
.
ts
;
if
(
diff
>
2u
s
&&
diff
<
-
2u
s
)
begin
$
display
(
"FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t"
,
now
,
e
.
ts
)
;
$
finish
(
1
)
;
end
end
end
prev
=
pulse
;
end
$
display
(
"SUCCESS: done"
)
;
$
finish
(
0
)
;
...
...
@@ -213,7 +213,7 @@ module dut_env
(
IVHDWishboneMaster
host
,
output
clk_sys
,
rst_sys_n
,
sfp_txp_o
,
sfp_txn_o
,
sfp_txp_o
,
sfp_txn_o
,
input
sfp_rxp_i
,
sfp_rxn_i
)
;
...
...
@@ -310,16 +310,16 @@ module dut_env
simple_tdc_driver
TDC
(
.
clk
(
clk_31m5_acam
)
,
.
addr
(
tdc_addr
)
,
.
data
(
tdc_data
)
,
.
wr
(
tdc_wr_n
)
,
.
rd
(
tdc_rd_n
)
,
.
ef1
(
tdc_ef1
)
,
.
ef2
(
tdc_ef2
)
,
.
tstart
(
tdc_start
)
,
.
intflag
(
tdc_int
)
)
;
.
clk
(
clk_31m5_acam
)
,
.
addr
(
tdc_addr
)
,
.
data
(
tdc_data
)
,
.
wr
(
tdc_wr_n
)
,
.
rd
(
tdc_rd_n
)
,
.
ef1
(
tdc_ef1
)
,
.
ef2
(
tdc_ef2
)
,
.
tstart
(
tdc_start
)
,
.
intflag
(
tdc_int
)
)
;
//---------------------------------------------------------------------------
// Fine Delay monitor
...
...
@@ -328,10 +328,10 @@ module dut_env
simple_fdelay_mon
FDL
(
.
len
(
fdl_len
)
,
.
val
(
fdl_val
)
,
.
pulse
(
fdl_pulse
)
)
;
.
len
(
fdl_len
)
,
.
val
(
fdl_val
)
,
.
pulse
(
fdl_pulse
)
)
;
//---------------------------------------------------------------------------
...
...
@@ -341,14 +341,14 @@ module dut_env
gc_sfp_i2c_adapter
SFP_I2C
(
.
clk_i
(
clk_125m_pll
)
,
.
rst_n_i
(
1'b1
)
,
.
scl_i
(
sfp_scl
)
,
.
sda_i
(
sfp_sda
)
,
.
sda_en_o
(
sfp_sda_en
)
,
.
sfp_det_valid_i
(
1'b1
)
,
.
sfp_data_i
(
128'h0123456789ABCDEF0123456789ABCDEF
)
)
;
.
clk_i
(
clk_125m_pll
)
,
.
rst_n_i
(
1'b1
)
,
.
scl_i
(
sfp_scl
)
,
.
sda_i
(
sfp_sda
)
,
.
sda_en_o
(
sfp_sda_en
)
,
.
sfp_det_valid_i
(
1'b1
)
,
.
sfp_data_i
(
128'h0123456789ABCDEF0123456789ABCDEF
)
)
;
assign
sfp_sda
=
(
sfp_sda_en
)
?
1'b0
:
1'bz
;
...
...
@@ -377,17 +377,17 @@ module dut_env
initial
begin
// Skip WR SoftPLL lock
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D1
.
OPMODE_dly
=
0
;
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D1
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D2
.
OPMODE_dly
=
0
;
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D2
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
end
// initial begin
endmodule
// dut_env
hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
View file @
47a61400
...
...
@@ -92,9 +92,9 @@ module main;
initial
begin
forever
begin
if
(
(
dev
!=
null
)
&&
(
dev
.
ready
)
)
dev
.
update
()
;
#
1u
s
;
if
(
(
dev
!=
null
)
&&
(
dev
.
ready
)
)
dev
.
update
()
;
#
1u
s
;
end
end
...
...
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