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White Rabbit Trigger Distribution
Commits
47a61400
Commit
47a61400
authored
Jun 27, 2019
by
Dimitris Lampridis
Browse files
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Plain Diff
hdl: cleanup tab characters in simulations
parent
8c8e6bf0
Expand all
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Showing
8 changed files
with
512 additions
and
512 deletions
+512
-512
wrtd_definitions.svh
hdl/testbench/include/wrtd_definitions.svh
+11
-11
wrtd_driver.svh
hdl/testbench/include/wrtd_driver.svh
+216
-216
wrtd_rep_cap.svh
hdl/testbench/include/wrtd_rep_cap.svh
+27
-27
wrtd_rule.svh
hdl/testbench/include/wrtd_rule.svh
+1
-1
dut_env.sv
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
+55
-55
main.sv
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
+107
-107
dut_env.sv
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
+92
-92
main.sv
hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
+3
-3
No files found.
hdl/testbench/include/wrtd_definitions.svh
View file @
47a61400
...
@@ -111,8 +111,8 @@ class WrtdTstamp;
...
@@ -111,8 +111,8 @@ class WrtdTstamp;
protected
uint32_t
frac
;
protected
uint32_t
frac
;
function
new
(
uint32_t
seconds
=
0
,
function
new
(
uint32_t
seconds
=
0
,
uint32_t
ns
=
0
,
uint32_t
ns
=
0
,
uint32_t
frac
=
0
)
;
uint32_t
frac
=
0
)
;
set
(
seconds
,
ns
,
frac
)
;
set
(
seconds
,
ns
,
frac
)
;
endfunction
// new
endfunction
// new
...
@@ -172,12 +172,12 @@ class WrtdId;
...
@@ -172,12 +172,12 @@ class WrtdId;
function
void
set
(
string
id
)
;
function
void
set
(
string
id
)
;
if
(
id
.
len
()
>
`WRTD_ID_LEN
)
if
(
id
.
len
()
>
`WRTD_ID_LEN
)
$
error
(
"length of string longer than the available storage"
)
;
$
error
(
"length of string longer than the available storage"
)
;
else
else
begin
begin
this
.
clear
()
;
this
.
clear
()
;
this
.
id
=
id
;
this
.
id
=
id
;
end
end
endfunction
// set
endfunction
// set
function
string
get
(
)
;
function
string
get
(
)
;
...
@@ -189,17 +189,17 @@ class WrtdId;
...
@@ -189,17 +189,17 @@ class WrtdId;
wrtd_data
d
;
wrtd_data
d
;
d
=
new
[
`WRTD_ID_LEN
/
4
]
;
d
=
new
[
`WRTD_ID_LEN
/
4
]
;
for
(
i
=
0
;
i
<
`WRTD_ID_LEN
/
4
;
i
++
)
for
(
i
=
0
;
i
<
`WRTD_ID_LEN
/
4
;
i
++
)
d
[
i
]
=
0
;
d
[
i
]
=
0
;
for
(
i
=
0
;
i
<
this
.
id
.
len
()
;
i
++
)
for
(
i
=
0
;
i
<
this
.
id
.
len
()
;
i
++
)
d
[
i
/
4
]
|=
this
.
id
[
i
]
<<
(
8
*
(
i
%
4
)
)
;
d
[
i
/
4
]
|=
this
.
id
[
i
]
<<
(
8
*
(
i
%
4
)
)
;
return
d
;
return
d
;
endfunction
// data_pack
endfunction
// data_pack
function
void
data_unpack
(
wrtd_data
data
)
;
function
void
data_unpack
(
wrtd_data
data
)
;
if
(
data
.
size
()
>
`WRTD_ID_LEN
/
4
)
if
(
data
.
size
()
>
`WRTD_ID_LEN
/
4
)
$
error
(
"length of data longer than the available storage"
)
;
$
error
(
"length of data longer than the available storage"
)
;
else
else
this
.
id
=
{
<<
32
{
{
<<
8
{
data
}
}
}
};
this
.
id
=
{
<<
32
{
{
<<
8
{
data
}
}
}
};
endfunction
// data_unpack
endfunction
// data_unpack
function
int
is_empty
(
)
;
function
int
is_empty
(
)
;
...
...
hdl/testbench/include/wrtd_driver.svh
View file @
47a61400
This diff is collapsed.
Click to expand it.
hdl/testbench/include/wrtd_rep_cap.svh
View file @
47a61400
...
@@ -47,9 +47,9 @@ virtual class WrtdRepCap;
...
@@ -47,9 +47,9 @@ virtual class WrtdRepCap;
task
mdisplay
(
string
str
)
;
task
mdisplay
(
string
str
)
;
string
tmp
;
string
tmp
;
if
(
this
.
name
==
""
)
if
(
this
.
name
==
""
)
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
else
else
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
$
display
(
tmp
)
;
$
display
(
tmp
)
;
endtask
// mdisplay
endtask
// mdisplay
...
@@ -83,9 +83,9 @@ virtual class WrtdRepCap;
...
@@ -83,9 +83,9 @@ virtual class WrtdRepCap;
function
void
set_enable
(
int
enable
)
;
function
void
set_enable
(
int
enable
)
;
if
(
enable
>
0
)
if
(
enable
>
0
)
this
.
enabled
=
1
;
this
.
enabled
=
1
;
else
else
this
.
enabled
=
0
;
this
.
enabled
=
0
;
endfunction
// set_enable
endfunction
// set_enable
function
void
set_disable
(
)
;
function
void
set_disable
(
)
;
...
@@ -110,17 +110,17 @@ class WrtdRepCapCollection;
...
@@ -110,17 +110,17 @@ class WrtdRepCapCollection;
task
mdisplay
(
string
str
)
;
task
mdisplay
(
string
str
)
;
string
tmp
;
string
tmp
;
if
(
this
.
name
==
""
)
if
(
this
.
name
==
""
)
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"<%t> %s"
,
$
realtime
,
str
)
;
else
else
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
tmp
=
$
sformatf
(
"[%s] <%t> %s"
,
this
.
name
,
$
realtime
,
str
)
;
$
display
(
tmp
)
;
$
display
(
tmp
)
;
endtask
// mdisplay
endtask
// mdisplay
function
void
validate_id
(
string
rep_cap_id
)
;
function
void
validate_id
(
string
rep_cap_id
)
;
if
(
rep_cap_id
.
len
()
>
`WRTD_ID_LEN
)
if
(
rep_cap_id
.
len
()
>
`WRTD_ID_LEN
)
$
error
(
"repeated capability name '%s' is too long"
,
rep_cap_id
)
;
$
error
(
"repeated capability name '%s' is too long"
,
rep_cap_id
)
;
if
(
rep_cap_id
.
len
()
==
0
)
if
(
rep_cap_id
.
len
()
==
0
)
$
error
(
"repeated capability name is null"
)
;
$
error
(
"repeated capability name is null"
)
;
endfunction
// validate_id
endfunction
// validate_id
function
int
add
(
string
rep_cap_id
)
;
function
int
add
(
string
rep_cap_id
)
;
...
@@ -131,21 +131,21 @@ class WrtdRepCapCollection;
...
@@ -131,21 +131,21 @@ class WrtdRepCapCollection;
idx
=
-
1
;
idx
=
-
1
;
for
(
i
=
0
;
i
<
this
.
collection
.
size
()
;
i
++
)
for
(
i
=
0
;
i
<
this
.
collection
.
size
()
;
i
++
)
begin
begin
if
(
this
.
collection
[
i
]
.
match
(
rep_cap_id
)
)
if
(
this
.
collection
[
i
]
.
match
(
rep_cap_id
)
)
begin
begin
$
error
(
"'%s' repeated capability ID already exists"
,
rep_cap_id
)
;
$
error
(
"'%s' repeated capability ID already exists"
,
rep_cap_id
)
;
return
-
1
;
return
-
1
;
end
end
if
(
idx
==
-
1
&&
this
.
collection
[
i
]
.
is_free
()
)
if
(
idx
==
-
1
&&
this
.
collection
[
i
]
.
is_free
()
)
idx
=
i
;
idx
=
i
;
end
end
if
(
idx
==
-
1
)
if
(
idx
==
-
1
)
$
error
(
"cannot add '%s' repeated capability, no space available"
,
rep_cap_id
)
;
$
error
(
"cannot add '%s' repeated capability, no space available"
,
rep_cap_id
)
;
else
else
this
.
collection
[
idx
]
.
set_rep_cap_id
(
rep_cap_id
)
;
this
.
collection
[
idx
]
.
set_rep_cap_id
(
rep_cap_id
)
;
return
idx
;
return
idx
;
endfunction
// add
endfunction
// add
...
@@ -156,8 +156,8 @@ class WrtdRepCapCollection;
...
@@ -156,8 +156,8 @@ class WrtdRepCapCollection;
validate_id
(
rep_cap_id
)
;
validate_id
(
rep_cap_id
)
;
for
(
i
=
0
;
i
<
this
.
collection
.
size
()
;
i
++
)
for
(
i
=
0
;
i
<
this
.
collection
.
size
()
;
i
++
)
if
(
this
.
collection
[
i
]
.
match
(
rep_cap_id
)
)
if
(
this
.
collection
[
i
]
.
match
(
rep_cap_id
)
)
return
i
;
return
i
;
return
-
1
;
return
-
1
;
endfunction
// find
endfunction
// find
...
@@ -168,15 +168,15 @@ class WrtdRepCapCollection;
...
@@ -168,15 +168,15 @@ class WrtdRepCapCollection;
idx
=
find
(
rep_cap_id
)
;
idx
=
find
(
rep_cap_id
)
;
if
(
idx
==
-
1
)
if
(
idx
==
-
1
)
begin
begin
$
error
(
"%s repeated capability ID cannot be removed because it does not exist"
,
rep_cap_id
)
;
$
error
(
"%s repeated capability ID cannot be removed because it does not exist"
,
rep_cap_id
)
;
return
idx
;
return
idx
;
end
end
if
(
this
.
collection
[
idx
]
.
is_enabled
(
)
)
if
(
this
.
collection
[
idx
]
.
is_enabled
(
)
)
$
error
(
"%s repeated capability ID cannot be removed because it is enabled"
,
rep_cap_id
)
;
$
error
(
"%s repeated capability ID cannot be removed because it is enabled"
,
rep_cap_id
)
;
else
else
this
.
collection
[
idx
]
.
clear
()
;
this
.
collection
[
idx
]
.
clear
()
;
return
idx
;
return
idx
;
endfunction
// remove
endfunction
// remove
...
...
hdl/testbench/include/wrtd_rule.svh
View file @
47a61400
...
@@ -38,7 +38,7 @@ class WrtdRule extends WrtdRepCap;
...
@@ -38,7 +38,7 @@ class WrtdRule extends WrtdRepCap;
protected
uint32_t
hold_off_ns
;
protected
uint32_t
hold_off_ns
;
protected
uint32_t
resync_period_ns
;
protected
uint32_t
resync_period_ns
;
protected
uint32_t
resync_factor
;
protected
uint32_t
resync_factor
;
int
hash_chain
;
int
hash_chain
;
protected
uint32_t
rx_events
;
protected
uint32_t
rx_events
;
protected
WrtdTstamp
rx_last
;
protected
WrtdTstamp
rx_last
;
protected
uint32_t
tx_events
;
protected
uint32_t
tx_events
;
...
...
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @
47a61400
...
@@ -226,14 +226,14 @@ module dut_env
...
@@ -226,14 +226,14 @@ module dut_env
gc_sfp_i2c_adapter
gc_sfp_i2c_adapter
SFP_I2C
SFP_I2C
(
(
.
clk_i
(
clk_125m_pll
)
,
.
clk_i
(
clk_125m_pll
)
,
.
rst_n_i
(
1'b1
)
,
.
rst_n_i
(
1'b1
)
,
.
scl_i
(
sfp_scl
)
,
.
scl_i
(
sfp_scl
)
,
.
sda_i
(
sfp_sda
)
,
.
sda_i
(
sfp_sda
)
,
.
sda_en_o
(
sfp_sda_en
)
,
.
sda_en_o
(
sfp_sda_en
)
,
.
sfp_det_valid_i
(
1'b1
)
,
.
sfp_det_valid_i
(
1'b1
)
,
.
sfp_data_i
(
128'h0123456789ABCDEF0123456789ABCDEF
)
.
sfp_data_i
(
128'h0123456789ABCDEF0123456789ABCDEF
)
)
;
)
;
assign
sfp_sda
=
(
sfp_sda_en
)
?
1'b0
:
1'bz
;
assign
sfp_sda
=
(
sfp_sda_en
)
?
1'b0
:
1'bz
;
...
@@ -243,66 +243,66 @@ module dut_env
...
@@ -243,66 +243,66 @@ module dut_env
always
@
(
negedge
clk_400m_adc
)
always
@
(
negedge
clk_400m_adc
)
begin
begin
#
625
ps
;
#
625
ps
;
if
(
adc_div
==
1
)
begin
if
(
adc_div
==
1
)
begin
adc0_fr
<=
~
adc0_fr
;
adc0_fr
<=
~
adc0_fr
;
adc_div
<=
0
;
adc_div
<=
0
;
end
end
else
begin
else
begin
adc_div
<=
adc_div
+
1
;
adc_div
<=
adc_div
+
1
;
end
end
end
end
always
@
(
posedge
adc0_fr
)
always
@
(
posedge
adc0_fr
)
begin
begin
if
((
adc0_data
>
400
)
||
(
adc0_data
<
-
400
))
begin
if
((
adc0_data
>
400
)
||
(
adc0_data
<
-
400
))
begin
adc_data_dir
=
~
adc_data_dir
;
adc_data_dir
=
~
adc_data_dir
;
end
end
if
(
adc_data_dir
==
0
)
begin
if
(
adc_data_dir
==
0
)
begin
adc0_data
=
adc0_data
+
8
;
adc0_data
=
adc0_data
+
8
;
end
end
else
begin
else
begin
adc0_data
=
adc0_data
-
8
;
adc0_data
=
adc0_data
-
8
;
end
end
adc0_dat_odd
=
{
4
{
adc0_data
[
13
]
}};
adc0_dat_odd
=
{
4
{
adc0_data
[
13
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
12
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
12
]
}};
#
1250
ps
;
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
11
]
}};
adc0_dat_odd
=
{
4
{
adc0_data
[
11
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
10
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
10
]
}};
#
1250
ps
;
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
9
]
}};
adc0_dat_odd
=
{
4
{
adc0_data
[
9
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
8
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
8
]
}};
#
1250
ps
;
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
7
]
}};
adc0_dat_odd
=
{
4
{
adc0_data
[
7
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
6
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
6
]
}};
#
1250
ps
;
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
5
]
}};
adc0_dat_odd
=
{
4
{
adc0_data
[
5
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
4
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
4
]
}};
#
1250
ps
;
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
3
]
}};
adc0_dat_odd
=
{
4
{
adc0_data
[
3
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
2
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
2
]
}};
#
1250
ps
;
#
1250
ps
;
adc0_dat_odd
=
{
4
{
adc0_data
[
1
]
}};
adc0_dat_odd
=
{
4
{
adc0_data
[
1
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
0
]
}};
adc0_dat_even
=
{
4
{
adc0_data
[
0
]
}};
#
1250
ps
;
#
1250
ps
;
adc0_dat_odd
=
{
4
{
1'b0
}};
adc0_dat_odd
=
{
4
{
1'b0
}};
adc0_dat_even
=
{
4
{
1'b0
}};
adc0_dat_even
=
{
4
{
1'b0
}};
end
end
initial
begin
initial
begin
// Skip WR SoftPLL lock
// Skip WR SoftPLL lock
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D1
.
OPMODE_dly
=
0
;
multiplier
.
D1
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D2
.
OPMODE_dly
=
0
;
multiplier
.
D2
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
multiplier
.
D3
.
OPMODE_dly
=
0
;
end
// initial begin
end
// initial begin
endmodule
// dut_env
endmodule
// dut_env
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @
47a61400
This diff is collapsed.
Click to expand it.
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
View file @
47a61400
...
@@ -41,8 +41,8 @@ module simple_tdc_driver
...
@@ -41,8 +41,8 @@ module simple_tdc_driver
)
;
)
;
typedef
struct
{
typedef
struct
{
int
channel
;
int
channel
;
time
ts
;
time
ts
;
}
acam_fifo_entry
;
}
acam_fifo_entry
;
acam_fifo_entry
pulses
[$]
;
acam_fifo_entry
pulses
[$]
;
...
@@ -71,30 +71,30 @@ module simple_tdc_driver
...
@@ -71,30 +71,30 @@ module simple_tdc_driver
time
now
;
time
now
;
wait
(
pulses
.
size
()
!=
0
)
wait
(
pulses
.
size
()
!=
0
)
;
;
t
=
pulses
.
pop_front
()
;
t
=
pulses
.
pop_front
()
;
now
=
$
time
;
now
=
$
time
;
if
(
t
.
ts
<=
now
)
if
(
t
.
ts
<=
now
)
$
display
(
"[DUT] <%t> TDC: pulse in the past (%t now=%t)!"
,
$
realtime
,
t
.
ts
,
now
)
;
$
display
(
"[DUT] <%t> TDC: pulse in the past (%t now=%t)!"
,
$
realtime
,
t
.
ts
,
now
)
;
else
else
begin
begin
const
int
fifo_n
=
t
.
channel
/
4
;
const
int
fifo_n
=
t
.
channel
/
4
;
logic
[
27
:
0
]
val
;
logic
[
27
:
0
]
val
;
#(
t
.
ts
-
now
)
;
#(
t
.
ts
-
now
)
;
val
[
27
:
26
]
=
t
.
channel
&
2'b11
;
val
[
27
:
26
]
=
t
.
channel
&
2'b11
;
val
[
25
:
18
]
=
start
;
val
[
25
:
18
]
=
start
;
val
[
17
]
=
1'b1
;
val
[
17
]
=
1'b1
;
val
[
16
:
0
]
=
(
t
.
ts
-
start_time
)
/
81
ps
;
val
[
16
:
0
]
=
(
t
.
ts
-
start_time
)
/
81
ps
;
$
display
(
"[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)"
,
$
display
(
"[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)"
,
$
realtime
,
t
.
ts
,
t
.
channel
,
start
,
val
[
16
:
0
]
,
start_time
)
;
$
realtime
,
t
.
ts
,
t
.
channel
,
start
,
val
[
16
:
0
]
,
start_time
)
;
fifos
[
t
.
channel
/
4
]
.
push_back
(
val
)
;
fifos
[
t
.
channel
/
4
]
.
push_back
(
val
)
;
end
end
end
end
initial
begin
initial
begin
...
@@ -110,34 +110,34 @@ module simple_tdc_driver
...
@@ -110,34 +110,34 @@ module simple_tdc_driver
always
@
(
posedge
clk
)
begin
always
@
(
posedge
clk
)
begin
start_rep
++;
start_rep
++;
if
(
start_rep
==
start_timer
)
begin
if
(
start_rep
==
start_timer
)
begin
start_rep
=
0
;
start_rep
=
0
;
if
(
restart_pulse
)
begin
if
(
restart_pulse
)
begin
start
=
1
;
start
=
1
;
restart_pulse
=
0
;
restart_pulse
=
0
;
start01
=
($
time
-
restart_time
)
/
81
ps
;
start01
=
($
time
-
restart_time
)
/
81
ps
;
end
end
else
begin
else
begin
start_time
=
$
time
;
start_time
=
$
time
;
start
++;
start
++;
end
end
end
end
end
end
always
@
(
rd
)
begin
always
@
(
rd
)
begin
rdata
<=
28'bz
;
rdata
<=
28'bz
;
if
(
rd
==
1'b0
)
begin
if
(
rd
==
1'b0
)
begin
if
(
addr
==
8
)
begin
if
(
addr
==
8
)
begin
rdata
<=
fifos
[
0
]
.
pop_front
()
;
rdata
<=
fifos
[
0
]
.
pop_front
()
;
end
end
else
if
(
addr
==
9
)
begin
else
if
(
addr
==
9
)
begin
rdata
<=
fifos
[
1
]
.
pop_front
()
;
rdata
<=
fifos
[
1
]
.
pop_front
()
;
end
end
else
if
(
addr
==
10
)
begin
else
if
(
addr
==
10
)
begin
rdata
<=
start01
;
rdata
<=
start01
;
end
end
else
begin
else
begin
$
display
(
"[DUT] <%t> invalid ACAM read 0x%x"
,
$
realtime
,
addr
)
;
$
display
(
"[DUT] <%t> invalid ACAM read 0x%x"
,
$
realtime
,
addr
)
;
end
end
end
end
end
end
...
@@ -160,8 +160,8 @@ module simple_fdelay_mon
...
@@ -160,8 +160,8 @@ module simple_fdelay_mon
)
;
)
;
typedef
struct
{
typedef
struct
{
int
channel
;
int
channel
;
time
ts
;
time
ts
;
}
fifo_entry
;
}
fifo_entry
;
fifo_entry
pulses
[$]
;
fifo_entry
pulses
[$]
;
...
@@ -180,28 +180,28 @@ module simple_fdelay_mon
...
@@ -180,28 +180,28 @@ module simple_fdelay_mon
prev
=
0
;
prev
=
0
;
while
(
pulses
.
size
()
!=
0
)
begin
while
(
pulses
.
size
()
!=
0
)
begin
@
pulse
;
@
pulse
;
now
=
$
time
;
now
=
$
time
;
$
display
(
"[FDEL] <%t> Pulse: len=%x, val=%x, out=%x"
,
now
,
len
,
val
,
pulse
)
;
$
display
(
"[FDEL] <%t> Pulse: len=%x, val=%x, out=%x"
,
now
,
len
,
val
,
pulse
)
;
for
(
int
i
=
0
;
i
<
4
;
i
++
)
begin
for
(
int
i
=
0
;
i
<
4
;
i
++
)
begin
if
(
prev
[
i
]
==
1'b0
&&
pulse
[
i
]
==
1'b1
)
begin
if
(
prev
[
i
]
==
1'b0
&&
pulse
[
i
]
==
1'b1
)
begin
automatic
fifo_entry
e
=
pulses
.
pop_front
()
;
automatic
fifo_entry
e
=
pulses
.
pop_front
()
;
automatic
time
diff
;
automatic
time
diff
;
$
display
(
"[FDEL] pulse on channel %0d"
,
i
)
;
$
display
(
"[FDEL] pulse on channel %0d"
,
i
)
;
if
(
e
.
channel
!=
i
)
begin
if
(
e
.
channel
!=
i
)
begin
$
display
(
"FAIL: [FDEL] Bad channel (expected %0d)"
,
e
.
channel
)
;
$
display
(
"FAIL: [FDEL] Bad channel (expected %0d)"
,
e
.
channel
)
;
$
finish
(
1
)
;
$
finish
(
1
)
;
end
end
diff
=
now
-
e
.
ts
;
diff
=
now
-
e
.
ts
;
if
(
diff
>
2u
s
&&
diff
<
-
2u
s
)
begin
if
(
diff
>
2u
s
&&
diff
<
-
2u
s
)
begin
$
display
(
"FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t"
,
now
,
e
.
ts
)
;
$
display
(
"FAIL: [FDEL] Bad timestamp: pulse at %t, expected at %t"
,
now
,
e
.
ts
)
;
$
finish
(
1
)
;
$
finish
(
1
)
;
end
end
end
end
end
end
prev
=
pulse
;
prev
=
pulse
;
end
end
$
display
(
"SUCCESS: done"
)
;
$
display
(
"SUCCESS: done"
)
;
$
finish
(
0
)
;
$
finish
(
0
)
;
...
@@ -213,7 +213,7 @@ module dut_env
...
@@ -213,7 +213,7 @@ module dut_env
(
(
IVHDWishboneMaster
host
,
IVHDWishboneMaster
host
,
output
clk_sys
,
rst_sys_n
,
output
clk_sys
,
rst_sys_n
,
sfp_txp_o
,
sfp_txn_o
,
sfp_txp_o
,
sfp_txn_o
,
input
sfp_rxp_i
,
sfp_rxn_i
input
sfp_rxp_i
,
sfp_rxn_i
)
;
)
;
...
@@ -310,16 +310,16 @@ module dut_env
...
@@ -310,16 +310,16 @@ module dut_env
simple_tdc_driver
simple_tdc_driver
TDC
TDC
(
(
.
clk
(
clk_31m5_acam
)
,
.
clk
(
clk_31m5_acam
)
,
.
addr
(
tdc_addr
)
,
.
addr
(
tdc_addr
)
,
.
data
(
tdc_data
)
,
.
data
(
tdc_data
)
,
.
wr
(
tdc_wr_n
)
,
.
wr
(
tdc_wr_n
)
,
.
rd
(
tdc_rd_n
)
,
.
rd
(
tdc_rd_n
)
,
.
ef1
(
tdc_ef1
)
,
.
ef1
(
tdc_ef1
)
,
.
ef2
(
tdc_ef2
)
,
.
ef2
(
tdc_ef2
)
,
.
tstart
(
tdc_start
)
,
.
tstart
(
tdc_start
)
,
.
intflag
(
tdc_int
)
.
intflag
(
tdc_int
)
)
;
)
;
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Fine Delay monitor
// Fine Delay monitor
...
@@ -328,10 +328,10 @@ module dut_env
...
@@ -328,10 +328,10 @@ module dut_env
simple_fdelay_mon
simple_fdelay_mon
FDL
FDL
(
(
.
len
(
fdl_len
)
,
.
len
(
fdl_len
)
,
.
val
(
fdl_val
)
,
.
val
(
fdl_val
)
,
.
pulse
(
fdl_pulse
)
.
pulse
(
fdl_pulse
)
)
;
)
;
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
...
@@ -341,14 +341,14 @@ module dut_env
...
@@ -341,14 +341,14 @@ module dut_env
gc_sfp_i2c_adapter
gc_sfp_i2c_adapter
SFP_I2C
SFP_I2C
(
(
.
clk_i
(
clk_125m_pll
)
,
.
clk_i
(
clk_125m_pll
)
,
.
rst_n_i
(
1'b1
)
,
.
rst_n_i
(
1'b1
)
,
.
scl_i
(
sfp_scl
)
,
.
scl_i
(
sfp_scl
)
,
.
sda_i
(
sfp_sda
)
,
.
sda_i
(
sfp_sda
)
,
.
sda_en_o
(
sfp_sda_en
)
,
.
sda_en_o
(
sfp_sda_en
)
,
.
sfp_det_valid_i
(
1'b1
)
,
.
sfp_det_valid_i
(
1'b1
)
,
.
sfp_data_i
(
128'h0123456789ABCDEF0123456789ABCDEF
)
.
sfp_data_i
(
128'h0123456789ABCDEF0123456789ABCDEF
)
)
;
)
;
assign
sfp_sda
=
(
sfp_sda_en
)
?
1'b0
:
1'bz
;
assign
sfp_sda
=
(
sfp_sda_en
)
?
1'b0
:
1'bz
;
...
@@ -377,17 +377,17 @@ module dut_env
...
@@ -377,17 +377,17 @@ module dut_env
initial
begin
initial
begin
// Skip WR SoftPLL lock
// Skip WR SoftPLL lock
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D1
.
OPMODE_dly
=
0
;
multiplier
.
D1
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D2
.
OPMODE_dly
=
0
;
multiplier
.
D2
.
OPMODE_dly
=
0
;
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
cmp_xwrc_board_svec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
multiplier
.
D3
.
OPMODE_dly
=
0
;
end
// initial begin
end
// initial begin
endmodule
// dut_env
endmodule
// dut_env
hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
View file @
47a61400
...
@@ -92,9 +92,9 @@ module main;
...
@@ -92,9 +92,9 @@ module main;
initial
begin
initial
begin
forever
begin
forever
begin
if
(
(
dev
!=
null
)
&&
(
dev
.
ready
)
)
if
(
(
dev
!=
null
)
&&
(
dev
.
ready
)
)
dev
.
update
()
;
dev
.
update
()
;
#
1u
s
;
#
1u
s
;
end
end
end
end
...
...
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