Commit 4d3a7c74 authored by Dimitris Lampridis's avatar Dimitris Lampridis

[hdl] remove ref clock div2 output from SVEC-TDC-FD

parent d7de6cf2
......@@ -171,7 +171,7 @@ entity wrtd_ref_svec_tdc_fd is
fp_led_column_o : out std_logic_vector(3 downto 0);
fp_gpio1_b : out std_logic; -- PPS output
fp_gpio2_b : out std_logic; -- Ref clock div2 output
fp_gpio2_b : out std_logic; -- not used
fp_gpio3_b : in std_logic; -- ext 10MHz clock input
fp_gpio4_b : in std_logic; -- ext PPS input
fp_term_en_o : out std_logic_vector(4 downto 1);
......@@ -380,7 +380,6 @@ architecture arch of wrtd_ref_svec_tdc_fd is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_ext_ref : std_logic;
signal tdc_clk_125m : std_logic;
signal dcm1_clk_ref_0 : std_logic;
......@@ -939,17 +938,9 @@ begin -- architecture arch
-- LED 5
svec_led(15 downto 14) <= c_LED_GREEN when pps_led = '1' else c_LED_OFF;
-- Div by 2 reference clock to LEMO connector
process(clk_ref_125m)
begin
if rising_edge(clk_ref_125m) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
-- Front panel IO configuration
fp_gpio1_b <= pps;
fp_gpio2_b <= clk_ref_div2;
fp_gpio2_b <= '0';
clk_ext_ref <= fp_gpio3_b;
pps_ext_in <= fp_gpio4_b;
fp_term_en_o <= (others => '0');
......
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