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White Rabbit Trigger Distribution
Commit 50865d0e authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] update to latest SPEC (renames template->base)

parent 8b15a770
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Showing with 26 additions and 14 deletions
spec @ 1b48d764
Subproject commit 7ebae5ae42c88abadec0b03b8634ba822d5b6d6a Subproject commit 1b48d76430920f62e871ce0e46bc61731f04d9b1
hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
View file @ 50865d0e
...@@ -35,6 +35,6 @@ except: ...@@ -35,6 +35,6 @@ except:
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)" syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_template_ucf = ['wr', 'ddr3', 'onewire', 'spi'] spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
ctrls = ["bank3_64b_32b"] ctrls = ["bank3_64b_32b"]
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ 50865d0e
...@@ -360,21 +360,26 @@ begin -- architecture arch ...@@ -360,21 +360,26 @@ begin -- architecture arch
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA), wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA)); wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
inst_spec_template : entity work.spec_template_wr inst_spec_base : entity work.spec_base_wr
generic map ( generic map (
g_WITH_VIC => TRUE, g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE, g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE, g_WITH_SPI => FALSE,
g_WITH_WR => TRUE, g_WITH_WR => TRUE,
g_WITH_DDR => TRUE, g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 64,
g_APP_OFFSET => c_METADATA_ADDR, g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 5, g_NUM_USER_IRQ => 5,
g_DPRAM_INITF => g_WRPC_INITF, g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 0,
g_FABRIC_IFACE => plain, g_FABRIC_IFACE => plain,
g_SIMULATION => g_SIMULATION) g_SIMULATION => f_int2bool(g_SIMULATION))
port map ( port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i, clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i, clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
gn_rst_n_i => gn_rst_n_i, gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i, gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i, gn_p2l_clk_p_i => gn_p2l_clk_p_i,
...@@ -408,12 +413,9 @@ begin -- architecture arch ...@@ -408,12 +413,9 @@ begin -- architecture arch
pcbrev_i => pcbrev_i, pcbrev_i => pcbrev_i,
led_act_o => led_act_o, led_act_o => led_act_o,
led_link_o => led_link_o, led_link_o => led_link_o,
button1_i => button1_n_i, button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o, plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o, plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o, pll25dac_cs_n_o => pll25dac_cs_n_o,
...@@ -449,13 +451,20 @@ begin -- architecture arch ...@@ -449,13 +451,20 @@ begin -- architecture arch
ddr_we_n_o => ddr_we_n_o, ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_ref_125m, ddr_dma_clk_i => clk_ref_125m,
ddr_dma_rst_n_i => rst_ref_125m_n, ddr_dma_rst_n_i => rst_ref_125m_n,
ddr_dma_wb_i => fmc0_wb_ddr_out, ddr_dma_wb_cyc_i => fmc0_wb_ddr_out.cyc,
ddr_dma_wb_o => fmc0_wb_ddr_in, ddr_dma_wb_stb_i => fmc0_wb_ddr_out.stb,
ddr_dma_wb_adr_i => fmc0_wb_ddr_out.adr,
ddr_dma_wb_sel_i => fmc0_wb_ddr_out.sel,
ddr_dma_wb_we_i => fmc0_wb_ddr_out.we,
ddr_dma_wb_dat_i => fmc0_wb_ddr_out.dat,
ddr_dma_wb_ack_o => fmc0_wb_ddr_in.ack,
ddr_dma_wb_stall_o => fmc0_wb_ddr_in.stall,
ddr_dma_wb_dat_o => fmc0_wb_ddr_in.dat,
ddr_wr_fifo_empty_o => ddr_wr_fifo_empty, ddr_wr_fifo_empty_o => ddr_wr_fifo_empty,
clk_sys_62m5_o => clk_sys_62m5, clk_62m5_sys_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n, rst_62m5_sys_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m, clk_125m_ref_o => clk_ref_125m,
rst_ref_125m_n_o => rst_ref_125m_n, rst_125m_ref_n_o => rst_ref_125m_n,
irq_user_i => irq_vector, irq_user_i => irq_vector,
wrf_src_o => eth_rx_in, wrf_src_o => eth_rx_in,
wrf_src_i => eth_rx_out, wrf_src_i => eth_rx_out,
...@@ -471,6 +480,9 @@ begin -- architecture arch ...@@ -471,6 +480,9 @@ begin -- architecture arch
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM), app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM)); app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
fmc0_wb_ddr_in.err <= '0';
fmc0_wb_ddr_in.rty <= '0';
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Primary wishbone crossbar -- Primary wishbone crossbar
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
......
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