Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit Trigger Distribution
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit Trigger Distribution
Commits
53772dc3
Commit
53772dc3
authored
Apr 11, 2019
by
Dimitris Lampridis
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
hdl: update SVEC TDC+FD reference design
parent
5de81645
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
27 additions
and
25 deletions
+27
-25
wrtd_ref_svec_tdc_fd.ucf
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
+2
-2
wrtd_ref_svec_tdc_fd.vhd
hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
+25
-23
No files found.
hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
View file @
53772dc3
...
...
@@ -284,8 +284,8 @@ NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "onewire_b" LOC = AC30;
NET "onewire_b" IOSTANDARD = "LVCMOS33";
NET "
carrier_
onewire_b" LOC = AC30;
NET "
carrier_
onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel LEDs
...
...
hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
View file @
53772dc3
...
...
@@ -334,8 +334,8 @@ architecture arch of wrtd_ref_svec_tdc_fd is
-- Primary Wishbone slave(s) offsets
constant
c_WB_SLAVE_VIC
:
integer
:
=
0
;
constant
c_WB_SLAVE_
TDC
:
integer
:
=
1
;
constant
c_WB_SLAVE_
FDL
:
integer
:
=
2
;
constant
c_WB_SLAVE_
FDL
:
integer
:
=
1
;
constant
c_WB_SLAVE_
TDC
:
integer
:
=
2
;
constant
c_WB_SLAVE_MT
:
integer
:
=
3
;
constant
c_WB_SLAVE_WRC
:
integer
:
=
4
;
constant
c_WB_DESC_SYN
:
integer
:
=
c_NUM_WB_SLAVES
;
...
...
@@ -350,13 +350,13 @@ architecture arch of wrtd_ref_svec_tdc_fd is
f_xwb_bridge_manual_sdb
(
x"0003ffff"
,
x"00030000"
);
constant
c_TDC_BRIDGE_SDB
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"0000
7FFF
"
,
x"00000000"
);
f_xwb_bridge_manual_sdb
(
x"0000
ffff
"
,
x"00000000"
);
-- Primary wishbone crossbar layout
constant
c_WB_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_SLAVES
+
1
downto
0
)
:
=
(
c_WB_SLAVE_VIC
=>
f_sdb_embed_device
(
c_XWB_VIC_SDB
,
x"00002000"
),
c_WB_SLAVE_FDL
=>
f_sdb_embed_device
(
c_FD_SDB_DEVICE
,
x"00008000"
),
c_WB_SLAVE_TDC
=>
f_sdb_embed_bridge
(
c_TDC_BRIDGE_SDB
,
x"00010000"
),
c_WB_SLAVE_FDL
=>
f_sdb_embed_device
(
c_FD_SDB_DEVICE
,
x"00018000"
),
c_WB_SLAVE_MT
=>
f_sdb_embed_device
(
c_MOCK_TURTLE_SDB
,
x"00020000"
),
c_WB_SLAVE_WRC
=>
f_sdb_embed_bridge
(
c_WRC_BRIDGE_SDB
,
x"00040000"
),
c_WB_DESC_SYN
=>
f_sdb_embed_synthesis
(
c_SDB_SYNTHESIS_INFO
),
...
...
@@ -552,12 +552,13 @@ begin -- architecture arch
cmp_sdb_crossbar
:
xwb_sdb_crossbar
generic
map
(
g_num_masters
=>
c_NUM_WB_MASTERS
,
g_num_slaves
=>
c_NUM_WB_SLAVES
,
g_registered
=>
TRUE
,
g_wraparound
=>
TRUE
,
g_layout
=>
c_WB_LAYOUT
,
g_sdb_addr
=>
c_SDB_ADDRESS
)
g_VERBOSE
=>
FALSE
,
g_NUM_MASTERS
=>
c_NUM_WB_MASTERS
,
g_NUM_SLAVES
=>
c_NUM_WB_SLAVES
,
g_REGISTERED
=>
TRUE
,
g_WRAPAROUND
=>
TRUE
,
g_LAYOUT
=>
c_WB_LAYOUT
,
g_SDB_ADDR
=>
c_SDB_ADDRESS
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
...
...
@@ -1000,11 +1001,12 @@ begin -- architecture arch
cmp_fmc1_wb_mux
:
xwb_crossbar
generic
map
(
g_num_masters
=>
2
,
g_num_slaves
=>
1
,
g_registered
=>
TRUE
,
g_address
=>
c_FMC_MUX_ADDR
,
g_mask
=>
c_FMC_MUX_MASK
)
g_VERBOSE
=>
FALSE
,
g_NUM_MASTERS
=>
2
,
g_NUM_SLAVES
=>
1
,
g_REGISTERED
=>
TRUE
,
g_ADDRESS
=>
c_FMC_MUX_ADDR
,
g_MASK
=>
c_FMC_MUX_MASK
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
...
...
@@ -1054,21 +1056,21 @@ begin -- architecture arch
line_o
=>
fp_led_line_o
,
line_oen_o
=>
fp_led_line_oen_o
);
-- LED
1
-- LED
4
svec_led
(
1
downto
0
)
<=
c_LED_GREEN
when
wr_led_link
=
'1'
else
c_LED_RED
;
-- LED 2
svec_led
(
3
downto
2
)
<=
c_LED_GREEN
when
tm_clk_aux_locked
(
0
)
=
'1'
else
c_LED_RED
;
-- LED 3
svec_led
(
3
downto
2
)
<=
c_LED_GREEN
when
tm_clk_aux_locked
(
1
)
=
'1'
else
c_LED_RED
;
-- LED 2
svec_led
(
5
downto
4
)
<=
c_LED_GREEN
when
tm_time_valid
=
'1'
else
c_LED_RED
;
-- LED
4
-- LED
1
svec_led
(
7
downto
6
)
<=
c_LED_RED_GREEN
when
vme_access_led
=
'1'
else
c_LED_OFF
;
-- LED
5
-- LED
8
svec_led
(
9
downto
8
)
<=
c_LED_RED_GREEN
when
wr_led_act
=
'1'
else
c_LED_OFF
;
-- LED 6
svec_led
(
11
downto
10
)
<=
c_LED_GREEN
when
tm_clk_aux_locked
(
1
)
=
'1'
else
c_LED_RED
;
-- LED 7
svec_led
(
11
downto
10
)
<=
c_LED_GREEN
when
tm_clk_aux_locked
(
0
)
=
'1'
else
c_LED_RED
;
-- LED 6
svec_led
(
13
downto
12
)
<=
c_LED_OFF
;
-- LED
8
-- LED
5
svec_led
(
15
downto
14
)
<=
c_LED_GREEN
when
pps_led
=
'1'
else
c_LED_OFF
;
-- Div by 2 reference clock to LEMO connector
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment