hdl: make it possible to synthesize list_tdc_fd with latest wr-cores and general-cores

545983b7 · Dimitris Lampridis · fcdea67a · 309cd51f · 8a82e727 · 545983b7
Commit 545983b7 authored Jul 20, 2018 by Dimitris Lampridis
7 changed files
--- a/fine-delay @ 309cd51f
+++ b/fine-delay @ 309cd51f
-Subproject commit 585895e26280b353ee92d5134573440b774f2223
+Subproject commit 309cd51f59efc8c10037f220dc22cde73ca9eda9
--- a/fmc-tdc @ 8a82e727
+++ b/fmc-tdc @ 8a82e727
-Subproject commit b10c63a4835259b730abbe0ef98b629e0ef29730
+Subproject commit 8a82e727483b3e65771c7a36d1371aba24a6db98
--- a/hdl/syn/svec/list_tdc_fd/.gitignore
+++ b/hdl/syn/svec/list_tdc_fd/.gitignore
+*
+!.gitignore
+!Manifest.py
--- a/hdl/syn/svec/list_tdc_fd/svec_list_tdc_fd.xise
+++ b/hdl/syn/svec/list_tdc_fd/svec_list_tdc_fd.xise
--- a/hdl/top/svec/list_tdc_fd/svec_top.ucf
+++ b/hdl/top/svec/list_tdc_fd/svec_top.ucf
@@ -16,8 +16,8 @@ NET "vme_iack_n_i" LOC = N1;
 NET "vme_ga_i[5]" LOC = M6;
 NET "vme_dtack_oe_o" LOC = T1;
 NET "vme_dtack_n_o" LOC = R5;
-NET "vme_ds_n_i[1]" LOC = Y7;
-NET "vme_ds_n_i[0]" LOC = Y6;
+NET "vme_ds_n_i[1]" LOC = Y6;
+NET "vme_ds_n_i[0]" LOC = Y7;
 NET "vme_data_oe_n_o" LOC = P1;
 NET "vme_data_dir_o" LOC = P2;
 NET "vme_berr_o" LOC = R3;
@@ -130,7 +130,7 @@ NET "sfp_los_i" LOC = W25;
 NET "sfp_mod_def0_b" LOC = Y26;
 NET "sfp_mod_def1_b" LOC = Y27;
 NET "sfp_mod_def2_b" LOC = AA24;
-#NET "sfp_rate_select_o" LOC = W24;
+NET "sfp_rate_select_b" LOC = W24;
 NET "sfp_tx_disable_o" LOC = AA25;
 NET "sfp_tx_fault_i" LOC = AA27;

@@ -171,6 +171,14 @@ NET "uart_rxd_i" LOC = U25;
 #----------------------------------------
 NET "tempid_dq_b" LOC = AC30;

+#----------------------------------------
+# Carrier I2C EEPROM
+#----------------------------------------
+NET "carrier_scl_b" LOC = AC29;
+NET "carrier_sda_b" LOC = AA30;
+NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
+NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
+
 #===============================================================================
 # IO Standard Constraints
 #===============================================================================
@@ -374,14 +382,14 @@ NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
 NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";


-net "dbg_led0_o" LOC="u7";
-net "dbg_led0_o" IOSTANDARD = "LVCMOS33"; 
-net "dbg_led1_o" LOC="r6";
-net "dbg_led1_o" IOSTANDARD = "LVCMOS33"; 
-net "dbg_led2_o" LOC="af1";
-net "dbg_led2_o" IOSTANDARD = "LVCMOS33"; 
-net "dbg_led3_o" LOC="ag1";
-net "dbg_led3_o" IOSTANDARD = "LVCMOS33"; 
+#net "dbg_led0_o" LOC="u7";
+#net "dbg_led0_o" IOSTANDARD = "LVCMOS33";
+#net "dbg_led1_o" LOC="r6";
+#net "dbg_led1_o" IOSTANDARD = "LVCMOS33";
+#net "dbg_led2_o" LOC="af1";
+#net "dbg_led2_o" IOSTANDARD = "LVCMOS33";
+#net "dbg_led3_o" LOC="ag1";
+#net "dbg_led3_o" IOSTANDARD = "LVCMOS33";

 # ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
 NET "fmc0_tdc_acam_refclk_p_i" LOC = "H15";

--- a/hdl/top/svec/list_tdc_fd/svec_top.vhd
+++ b/hdl/top/svec/list_tdc_fd/svec_top.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2014-04-01
-- Last update: 2018-07-04
+-- Last update: 2018-07-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -82,10 +82,10 @@ entity svec_top is
    fp_gpio3_b : inout std_logic;
    fp_gpio4_b : inout std_logic;

-    dbg_led0_o : out std_logic;
-    dbg_led1_o : out std_logic;
-    dbg_led2_o : out std_logic;
-    dbg_led3_o : out std_logic;
+    --dbg_led0_o : out std_logic;
+    --dbg_led1_o : out std_logic;
+    --dbg_led2_o : out std_logic;
+    --dbg_led3_o : out std_logic;

    carrier_scl_b : inout std_logic;
    carrier_sda_b : inout std_logic;
@@ -395,7 +395,6 @@ begin
      g_simulation               => g_simulation,
      g_with_wr_phy              => true,
      g_double_wrnode_core_clock => false,
-      g_with_white_rabbit        => true,
      g_mt_config                => c_mt_config)
    port map (
      rst_n_a_i           => rst_n_a_i,

--- a/hdl/top/svec/node_template/svec_node_template.vhd
+++ b/hdl/top/svec/node_template/svec_node_template.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Włostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2014-04-01
-- Last update: 2018-07-04
+-- Last update: 2018-07-20
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -821,13 +821,7 @@ begin

      clk_ref_i        => clk_125m_pllref,

-      tmi_i.link_up    => tm_link_up,
-      tmi_i.dac_value  => tm_dac_value,
-      tmi_i.dac_wr     => tm_dac_wr,
-      tmi_i.time_valid => tm_time_valid,
-      tmi_i.tai        => tm_tai,
-      tmi_i.cycles     => tm_cycles,
-      tmi_i.aux_locked => tm_clk_aux_locked,
+      tm_i             => tm,

      hmq_in_irq_o     => mt_hmq_in_irq,
      hmq_out_irq_o    => mt_hmq_out_irq,
@@ -1002,6 +996,8 @@ begin
  tm.tai                    <= tm_tai;
  tm.time_valid             <= tm_time_valid;
  tm.link_up                <= tm_link_up;
+  tm.dac_wr                 <= tm_dac_wr(0);
+  tm.dac_value              <= tm_dac_value;
  tm.aux_locked(1 downto 0) <= tm_clk_aux_locked;
  tm.aux_locked(7 downto 6) <= (others => '0');