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White Rabbit Trigger Distribution
Commits
578850fb
Commit
578850fb
authored
Jul 12, 2019
by
Dimitris Lampridis
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[hdl] convert WRTD SPEC FMC-ADC reference node to the Convention (synthesized, not tested)
parent
308fb6b2
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6 changed files
with
181 additions
and
602 deletions
+181
-602
.gitmodules
.gitmodules
+3
-0
general-cores
dependencies/general-cores
+1
-1
spec
dependencies/spec
+1
-0
wrtd_ref_spec150t_adc.ucf
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
+14
-14
Manifest.py
hdl/top/wrtd_ref_spec150t_adc/Manifest.py
+1
-0
wrtd_ref_spec150t_adc.vhd
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
+161
-587
No files found.
.gitmodules
View file @
578850fb
...
...
@@ -28,3 +28,6 @@
[submodule "dependencies/gn4124-core"]
path = dependencies/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
[submodule "dependencies/spec"]
path = dependencies/spec
url = https://ohwr.org/project/spec.git
general-cores
@
c010febb
Subproject commit
28cd756047ce9f85cf7c134367c7439f1189114d
Subproject commit
c010febba58a1b616c971f6fd8c953df51e411b6
spec
@
ed94f859
Subproject commit ed94f8594009fda6deafde22532fb48c321792b9
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @
578850fb
...
...
@@ -222,7 +222,7 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "cmp_xwrc_board_spec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
NET "
*/
cmp_xwrc_board_spec/*/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
NET "gn_p2l_clk_n_i" TNM_NET = "p2l_clk";
...
...
@@ -252,13 +252,13 @@ NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Declaration of domains
NET "c
lk_sys_62m5"
TNM_NET = sys_clk_62_5;
NET "c
lk_ref_125m"
TNM_NET = clk_125m_pllref;
NET "c
lk_ddr_333m"
TNM_NET = ddr_clk_333m;
NET "
cmp_xwrc_board_spec/clk_pll_dmtd"
TNM_NET = clk_dmtd;
NET "
cmp_xwrc_board_spec/phy8_to_wrc_rx_clk"
TNM_NET = phy_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk;
NET "c
mp_spec_template_wr/clk_sys_62m5"
TNM_NET = sys_clk_62_5;
NET "c
mp_spec_template_wr/clk_ref_125m"
TNM_NET = clk_125m_pllref;
NET "c
mp_spec_template_wr/clk_ddr_333m"
TNM_NET = ddr_clk_333m;
NET "
*/cmp_xwrc_board_spec/clk_pll_dmtd"
TNM_NET = clk_dmtd;
NET "
*/cmp_xwrc_board_spec/phy8_to_wrc_rx_clk"
TNM_NET = phy_clk;
NET "
*/
cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "
*/
cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk";
...
...
@@ -479,17 +479,17 @@ TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "
cmp_ddr0_ctrl_bank
/*/c?_pll_lock" TIG;
NET "
cmp_ddr0_ctrl_bank
/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "
cmp_ddr0_ctrl_bank
/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "
cmp_ddr0_ctrl_bank
/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "
*/cmp_ddr_ctrl_bank3
/*/c?_pll_lock" TIG;
NET "
*/cmp_ddr_ctrl_bank3
/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "
*/cmp_ddr_ctrl_bank3
/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "
*/cmp_ddr_ctrl_bank3
/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "
ddr0
_rst" TPTHRU = ddr_rst;
NET "
cmp_spec_template_wr/ddr
_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
...
...
@@ -498,7 +498,7 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "
cmp_ddr0_ctrl_bank
/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
NET "
*/cmp_ddr_ctrl_bank3
/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk;
TIMEGRP "ddr0_clk" = "ddr0_clk_333m" "ddr0_bank3_clk";
...
...
hdl/top/wrtd_ref_spec150t_adc/Manifest.py
View file @
578850fb
...
...
@@ -15,6 +15,7 @@ modules = {
"https://ohwr.org/project/mock-turtle.git"
,
"https://ohwr.org/project/ddr3-sp6-core.git"
,
"https://ohwr.org/project/gn4124-core.git"
,
"https://ohwr.org/project/spec.git"
,
"https://ohwr.org/project/fmc-adc-100m14b4cha-gw.git"
,
],
}
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @
578850fb
...
...
@@ -33,18 +33,11 @@ use ieee.numeric_std.all;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
gn4124_core_pkg
.
all
;
use
work
.
carrier_csr_wbgen2_pkg
.
all
;
use
work
.
mt_mqueue_pkg
.
all
;
use
work
.
mock_turtle_pkg
.
all
;
use
work
.
synthesis_descriptor
.
all
;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_spec_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
fmc_adc_mezzanine_pkg
.
all
;
use
work
.
ddr3_ctrl_pkg
.
all
;
entity
wrtd_ref_spec150t_adc
is
generic
(
...
...
@@ -199,8 +192,6 @@ entity wrtd_ref_spec150t_adc is
fmc0_adc_one_wire_b
:
inout
std_logic
;
-- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
-- FMC slot management
fmc0_prsnt_m2c_n_i
:
in
std_logic
;
...
...
@@ -216,45 +207,29 @@ architecture arch of wrtd_ref_spec150t_adc is
-- Constants
-----------------------------------------------------------------------------
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant
c_WRPC_PLL_CONFIG
:
t_auxpll_cfg_array
:
=
(
0
=>
(
enabled
=>
TRUE
,
bufg_en
=>
TRUE
,
divide
=>
3
),
others
=>
c_AUXPLL_CFG_DEFAULT
);
-- SPEC carrier CSR constants
constant
c_CARRIER_TYPE
:
std_logic_vector
(
15
downto
0
)
:
=
X"0001"
;
-- Number of masters attached to the primary wishbone crossbar
constant
c_NUM_WB_MASTERS
:
integer
:
=
1
;
-- Number of slaves attached to the primary wishbone crossbar
constant
c_NUM_WB_SLAVES
:
integer
:
=
3
+
4
;
constant
c_NUM_WB_SLAVES
:
integer
:
=
3
;
-- Primary Wishbone master(s) offsets
constant
c_WB_MASTER_GENNUM
:
integer
:
=
0
;
-- Primary Wishbone slave(s) offsets
constant
c_WB_SLAVE_SPEC_CSR
:
integer
:
=
0
;
constant
c_WB_SLAVE_VIC
:
integer
:
=
1
;
constant
c_WB_SLAVE_BASE
:
integer
:
=
2
;
constant
c_WB_SLAVE_DMA
:
integer
:
=
c_WB_SLAVE_BASE
+
0
;
constant
c_WB_SLAVE_DMA_EIC
:
integer
:
=
c_WB_SLAVE_BASE
+
1
;
constant
c_WB_SLAVE_FMC_ADC
:
integer
:
=
c_WB_SLAVE_BASE
+
2
;
constant
c_WB_SLAVE_MT
:
integer
:
=
c_WB_SLAVE_BASE
+
0
+
3
;
constant
c_WB_SLAVE_WRC
:
integer
:
=
c_WB_SLAVE_BASE
+
1
+
3
;
constant
c_WB_DESC_SYN
:
integer
:
=
c_WB_SLAVE_BASE
+
2
+
3
;
constant
c_WB_DESC_URL
:
integer
:
=
c_WB_SLAVE_BASE
+
3
+
3
;
constant
c_WB_SLAVE_METADATA
:
integer
:
=
0
;
constant
c_WB_SLAVE_FMC_ADC
:
integer
:
=
1
;
constant
c_WB_SLAVE_MT
:
integer
:
=
2
;
constant
c_WB_DESC_SYN
:
integer
:
=
c_NUM_WB_SLAVES
+
0
;
constant
c_WB_DESC_URL
:
integer
:
=
c_NUM_WB_SLAVES
+
1
;
-- sdb header address on primary crossbar
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"000
0
0000"
;
constant
c_SDB_ADDRESS
:
t_wishbone_address
:
=
x"000
4
0000"
;
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant
c_wrc_bridge_sdb
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"0003ffff"
,
x"00030000"
);
-- Convertion metadata base address
constant
c_METADATA_ADDR
:
t_wishbone_address
:
=
x"0000_2000"
;
constant
c_WB_
SPEC_CSR
_SDB
:
t_sdb_device
:
=
(
constant
c_WB_
METADATA
_SDB
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
...
...
@@ -262,77 +237,24 @@ architecture arch of wrtd_ref_spec150t_adc is
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000
001
F"
,
addr_last
=>
x"000000000000
1FF
F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000603"
,
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-SPEC-CSR "
)));
date
=>
x"20190710"
,
name
=>
"WB-METADATA "
)));
constant
c_FMC_BRIDGE_SDB
:
t_sdb_bridge
:
=
f_xwb_bridge_manual_sdb
(
x"00001fff"
,
x"00000000"
);
constant
c_WB_DMA_CTRL_SDB
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_SDB_ENDIAN_BIG
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000003F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"00000601"
,
version
=>
x"00000001"
,
date
=>
x"20121116"
,
name
=>
"WB-DMA.Control "
)));
constant
c_WB_DMA_EIC_SDB
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"01"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_SDB_ENDIAN_BIG
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
sdb_component
=>
(
addr_first
=>
x"0000000000000000"
,
addr_last
=>
x"000000000000000F"
,
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"d5735ab4"
,
-- echo "WB-DMA.EIC " | md5sum | cut -c1-8
version
=>
x"00000001"
,
date
=>
x"20131204"
,
name
=>
"WB-DMA.EIC "
)));
-- Primary wishbone crossbar layout
constant
c_WB_LAYOUT
:
t_sdb_record_array
(
c_NUM_WB_SLAVES
+
1
downto
0
)
:
=
(
c_WB_SLAVE_SPEC_CSR
=>
f_sdb_embed_device
(
c_WB_SPEC_CSR_SDB
,
x"00001000"
),
c_WB_SLAVE_VIC
=>
f_sdb_embed_device
(
c_XWB_VIC_SDB
,
x"00001200"
),
c_WB_SLAVE_DMA
=>
f_sdb_embed_device
(
c_WB_DMA_CTRL_SDB
,
x"00002000"
),
c_WB_SLAVE_DMA_EIC
=>
f_sdb_embed_device
(
c_WB_DMA_EIC_SDB
,
x"00002200"
),
c_WB_SLAVE_FMC_ADC
=>
f_sdb_embed_bridge
(
c_FMC_BRIDGE_SDB
,
x"00004000"
),
c_WB_SLAVE_MT
=>
f_sdb_embed_device
(
c_MOCK_TURTLE_SDB
,
x"00020000"
),
c_WB_SLAVE_WRC
=>
f_sdb_embed_bridge
(
c_wrc_bridge_sdb
,
x"00040000"
),
c_WB_SLAVE_METADATA
=>
f_sdb_embed_device
(
c_WB_METADATA_SDB
,
c_METADATA_ADDR
),
c_WB_SLAVE_FMC_ADC
=>
f_sdb_embed_bridge
(
c_FMC_BRIDGE_SDB
,
x"0000_4000"
),
c_WB_SLAVE_MT
=>
f_sdb_embed_device
(
c_MOCK_TURTLE_SDB
,
x"0002_0000"
),
c_WB_DESC_SYN
=>
f_sdb_embed_synthesis
(
c_SDB_SYNTHESIS_INFO
),
c_WB_DESC_URL
=>
f_sdb_embed_repo_url
(
c_SDB_REPO_URL
));
-- not really used, will be reprogrammed by software
constant
c_VIC_VECTOR_TABLE
:
t_wishbone_address_array
(
0
to
5
)
:
=
(
0
=>
x"00005500"
,
-- FMC EIC
1
=>
x"00002200"
,
-- DMA EIC
2
=>
x"00020000"
,
-- MT Mqueue in interrupt
3
=>
x"00020001"
,
-- MT Mqueue out interrupt
4
=>
x"00020002"
,
-- MT Console interrupt
5
=>
x"00020003"
);
-- MT Notify interrupt
constant
c_FMC_MUX_ADDR
:
t_wishbone_address_array
(
0
downto
0
)
:
=
(
0
=>
x"00000000"
);
constant
c_FMC_MUX_MASK
:
t_wishbone_address_array
(
0
downto
0
)
:
=
(
0
=>
x"10000000"
);
constant
c_MT_CONFIG
:
t_mt_config
:
=
(
app_id
=>
x"115790d1"
,
...
...
@@ -372,29 +294,9 @@ architecture arch of wrtd_ref_spec150t_adc is
-- Clocks and resets
signal
clk_sys_62m5
:
std_logic
;
signal
clk_ref_125m
:
std_logic
;
signal
sys_clk_pll_locked
:
std_logic
;
signal
clk_ddr_333m
:
std_logic
;
signal
clk_pll_aux
:
std_logic_vector
(
3
downto
0
);
signal
rst_pll_aux_n
:
std_logic_vector
(
3
downto
0
)
:
=
(
others
=>
'0'
);
signal
rst_sys_62m5_n
:
std_logic
:
=
'0'
;
signal
rst_ref_125m_n
:
std_logic
:
=
'0'
;
signal
rst_ddr_333m_n
:
std_logic
:
=
'0'
;
signal
sw_rst_fmc
:
std_logic
:
=
'1'
;
signal
sw_rst_fmc_sync
:
std_logic
:
=
'1'
;
signal
fmc_rst_ref_125m_n
:
std_logic
:
=
'0'
;
signal
fmc_rst_sys_n
:
std_logic
:
=
'0'
;
signal
ddr0_rst
:
std_logic
:
=
'1'
;
attribute
keep
:
string
;
attribute
keep
of
clk_sys_62m5
:
signal
is
"TRUE"
;
attribute
keep
of
clk_ref_125m
:
signal
is
"TRUE"
;
attribute
keep
of
clk_ddr_333m
:
signal
is
"TRUE"
;
attribute
keep
of
ddr0_rst
:
signal
is
"TRUE"
;
-- GN4124
signal
gn4124_status
:
std_logic_vector
(
31
downto
0
);
signal
gn4124_access
:
std_logic
;
-- Wishbone buse(s) from master(s) to crossbar slave port(s)
signal
cnx_master_out
:
t_wishbone_master_out_array
(
c_NUM_WB_MASTERS
-1
downto
0
);
...
...
@@ -408,38 +310,6 @@ architecture arch of wrtd_ref_spec150t_adc is
signal
gn_wb_ddr_in
:
t_wishbone_master_in
;
signal
gn_wb_ddr_out
:
t_wishbone_master_out
;
-- Interrupts and status
signal
dma_irq
:
std_logic_vector
(
1
downto
0
);
signal
fmc_host_irq
:
std_logic_vector
(
0
downto
0
)
:
=
"0"
;
signal
mt_hmq_in_irq
:
std_logic
;
signal
mt_hmq_out_irq
:
std_logic
;
signal
mt_console_irq
:
std_logic
;
signal
mt_notify_irq
:
std_logic
;
signal
vic_master_irq
:
std_logic
;
-- Front panel LED control
signal
led_red
:
std_logic
;
signal
led_green
:
std_logic
;
-- SFP
signal
sfp_sda_in
:
std_logic
;
signal
sfp_sda_out
:
std_logic
;
signal
sfp_scl_in
:
std_logic
;
signal
sfp_scl_out
:
std_logic
;
-- OneWire
signal
onewire_data
:
std_logic
;
signal
onewire_oe
:
std_logic
;
-- LEDs and GPIO
signal
pps
:
std_logic
;
signal
pps_led
:
std_logic
;
signal
pps_ext_in
:
std_logic
;
signal
svec_led
:
std_logic_vector
(
15
downto
0
);
signal
wr_led_link
:
std_logic
;
signal
wr_led_act
:
std_logic
;
-- MT endpoints
signal
rmq_endpoint_out
:
t_mt_rmq_endpoint_iface_out
;
signal
rmq_endpoint_in
:
t_mt_rmq_endpoint_iface_in
;
...
...
@@ -462,28 +332,18 @@ architecture arch of wrtd_ref_spec150t_adc is
signal
fmc_dp_wb_out
:
t_wishbone_master_out
;
signal
fmc_dp_wb_in
:
t_wishbone_master_in
;
-- WRPC TM interface and
aux clock
s
-- WRPC TM interface and
statu
s
signal
tm_link_up
:
std_logic
;
signal
tm_tai
:
std_logic_vector
(
39
downto
0
);
signal
tm_cycles
:
std_logic_vector
(
27
downto
0
);
signal
tm_time_valid
:
std_logic
;
signal
tm_clk_aux_lock_en
:
std_logic_vector
(
1
downto
0
);
signal
tm_clk_aux_locked
:
std_logic_vector
(
1
downto
0
)
:
=
"00"
;
signal
tm_dac_value
:
std_logic_vector
(
23
downto
0
);
signal
tm_dac_wr
:
std_logic_vector
(
1
downto
0
);
signal
tm_time_valid_sync
:
std_logic
;
signal
wrabbit_en
:
std_logic
;
signal
pps_led
:
std_logic
;
-- MT TM interface
signal
tm
:
t_mt_timing_if
;
-- IO for CSR registers
signal
csr_regin
:
t_carrier_csr_in_registers
;
signal
csr_regout
:
t_carrier_csr_out_registers
;
constant
g_FMC0_MULTISHOT_RAM_SIZE
:
natural
:
=
2048
;
constant
g_FMC0_CALIB_SOFT_IP
:
string
:
=
"TRUE"
;
-- Wishbone bus from cross-clocking module to FMC0 mezzanine
signal
cnx_fmc0_sync_master_out
:
t_wishbone_master_out
;
signal
cnx_fmc0_sync_master_in
:
t_wishbone_master_in
;
...
...
@@ -499,163 +359,136 @@ architecture arch of wrtd_ref_spec150t_adc is
signal
fmc0_wb_ddr_out
:
t_wishbone_master_data64_out
;
-- Interrupts and status
signal
ddr0_wr_fifo_empty
:
std_logic
;
signal
ddr0_wr_fifo_empty_sync
:
std_logic
;
signal
fmc0_irq
:
std_logic
;
signal
tm_time_valid_sync
:
std_logic
;
-- Conversion of g_simulation to string needed for DDR controller
function
fmc0_f_int2string
(
n
:
natural
)
return
string
is
begin
if
n
=
0
then
return
"FALSE"
;
else
return
"TRUE "
;
end
if
;
end
;
constant
c_FMC0_SIMULATION_STR
:
string
:
=
fmc0_f_int2string
(
g_SIMULATION
);
-- DDR
signal
ddr0_status
:
std_logic_vector
(
31
downto
0
);
signal
ddr0_calib_done
:
std_logic
;
signal
ddr0_addr_cnt
:
unsigned
(
31
downto
0
);
signal
ddr0_dat_cyc_d
:
std_logic
;
signal
ddr0_addr_cnt_en
:
std_logic
;
-- Interrupts and status
signal
dma_eic_irq
:
std_logic
;
-- Resync interrupts to sys domain
signal
dma_irq_sync
:
std_logic_vector
(
1
downto
0
);
signal
ddr_wr_fifo_empty_sync
:
std_logic
;
signal
fmc_irq_sync
:
std_logic
;
signal
ddr0_wr_fifo_empty
:
std_logic
;
signal
fmc0_irq
:
std_logic
;
signal
irq_vector
:
std_logic_vector
(
4
downto
0
);
signal
gn4124_access
:
std_logic
;
begin
-- architecture arch
------------------------------------------------------------------------------
-- Reset logic
------------------------------------------------------------------------------
sys_clk_pll_locked
<=
'1'
;
-- reset for mezzanine
-- including soft reset, with re-sync from 62.5MHz domain
-- and registers to help with timing
cmp_fmc_sw_reset_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_125m
,
rst_n_i
=>
'1'
,
data_i
=>
sw_rst_fmc
,
synced_o
=>
sw_rst_fmc_sync
);
fmc_rst_ref_125m_n
<=
rst_ref_125m_n
and
not
sw_rst_fmc_sync
;
fmc_rst_sys_n
<=
rst_sys_62m5_n
and
not
sw_rst_fmc
;
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr0_rst
<=
not
rst_ddr_333m_n
or
sw_rst_fmc
;
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr
:
entity
work
.
carrier_csr
cmp_xwb_metadata
:
entity
work
.
xwb_metadata
generic
map
(
g_VENDOR_ID
=>
x"0000_10DC"
,
g_DEVICE_ID
=>
x"574E_0001"
,
-- WRTD Node (WN) 1
g_VERSION
=>
x"0100_0000"
,
g_CAPABILITIES
=>
x"0000_0000"
,
g_COMMIT_ID
=>
(
others
=>
'0'
))
port
map
(
rst_n_i
=>
rst_sys_62m5_n
,
clk_sys_i
=>
clk_sys_62m5
,
wb_adr_i
=>
cnx_slave_in
(
c_WB_SLAVE_SPEC_CSR
)
.
adr
(
3
downto
2
),
-- cnx_slave_in.adr is byte address
wb_dat_i
=>
cnx_slave_in
(
c_WB_SLAVE_SPEC_CSR
)
.
dat
,
wb_dat_o
=>
cnx_slave_out
(
c_WB_SLAVE_SPEC_CSR
)
.
dat
,
wb_cyc_i
=>
cnx_slave_in
(
c_WB_SLAVE_SPEC_CSR
)
.
cyc
,
wb_sel_i
=>
cnx_slave_in
(
c_WB_SLAVE_SPEC_CSR
)
.
sel
,
wb_stb_i
=>
cnx_slave_in
(
c_WB_SLAVE_SPEC_CSR
)
.
stb
,
wb_we_i
=>
cnx_slave_in
(
c_WB_SLAVE_SPEC_CSR
)
.
we
,
wb_ack_o
=>
cnx_slave_out
(
c_WB_SLAVE_SPEC_CSR
)
.
ack
,
wb_stall_o
=>
open
,
regs_i
=>
csr_regin
,
regs_o
=>
csr_regout
);
csr_regin
.
carrier_pcb_rev_i
<=
pcbrev_i
;
csr_regin
.
carrier_reserved_i
<=
(
others
=>
'0'
);
csr_regin
.
carrier_type_i
<=
c_CARRIER_TYPE
;
csr_regin
.
stat_fmc_pres_i
<=
fmc0_prsnt_m2c_n_i
;
csr_regin
.
stat_p2l_pll_lck_i
<=
gn4124_status
(
0
);
csr_regin
.
stat_sys_pll_lck_i
<=
sys_clk_pll_locked
;
csr_regin
.
stat_ddr3_cal_done_i
<=
ddr0_calib_done
;
led_red
<=
csr_regout
.
ctrl_led_red_o
;
led_green
<=
csr_regout
.
ctrl_led_green_o
;
sw_rst_fmc
<=
csr_regout
.
rst_fmc0_o
;
-- Unused wishbone signals
cnx_slave_out
(
c_WB_SLAVE_SPEC_CSR
)
.
err
<=
'0'
;
cnx_slave_out
(
c_WB_SLAVE_SPEC_CSR
)
.
rty
<=
'0'
;
cnx_slave_out
(
c_WB_SLAVE_SPEC_CSR
)
.
stall
<=
'0'
;
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
wb_i
=>
cnx_slave_in
(
c_WB_SLAVE_METADATA
),
wb_o
=>
cnx_slave_out
(
c_WB_SLAVE_METADATA
));
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core
:
xwb_gn4124_core
cmp_spec_template_wr
:
entity
work
.
spec_template_wr
generic
map
(
g_W
BM_TO_WB_FIFO_SIZE
=>
16
,
g_W
BM_TO_WB_FIFO_FULL_THRES
=>
12
,
g_W
BM_FROM_WB_FIFO_SIZE
=>
16
,
g_W
BM_FROM_WB_FIFO_FULL_THRES
=>
12
,
g_
P2L_FIFO_SIZE
=>
256
,
g_
P2L_FIFO_FULL_THRES
=>
175
,
g_
L2P_ADDR_FIFO_FULL_SIZE
=>
256
,
g_
L2P_ADDR_FIFO_FULL_THRES
=>
175
,
g_
L2P_DATA_FIFO_FULL_SIZE
=>
256
,
g_
L2P_DATA_FIFO_FULL_THRES
=>
175
)
g_W
ITH_VIC
=>
TRUE
,
g_W
ITH_ONEWIRE
=>
TRUE
,
g_W
ITH_SPI
=>
TRUE
,
g_W
ITH_WR
=>
TRUE
,
g_
WITH_DDR
=>
TRUE
,
g_
APP_OFFSET
=>
c_METADATA_ADDR
,
g_
NUM_USER_IRQ
=>
5
,
g_
DPRAM_INITF
=>
g_WRPC_INITF
,
g_
FABRIC_IFACE
=>
plain
,
g_
SIMULATION
=>
g_SIMULATION
)
port
map
(
rst_n_a_i
=>
gn_rst_n_i
,
status_o
=>
gn4124_status
,
p2l_clk_p_i
=>
gn_p2l_clk_p_i
,
p2l_clk_n_i
=>
gn_p2l_clk_n_i
,
p2l_data_i
=>
gn_p2l_data_i
,
p2l_dframe_i
=>
gn_p2l_dframe_i
,
p2l_valid_i
=>
gn_p2l_valid_i
,
p2l_rdy_o
=>
gn_p2l_rdy_o
,
p_wr_req_i
=>
gn_p_wr_req_i
,
p_wr_rdy_o
=>
gn_p_wr_rdy_o
,
rx_error_o
=>
gn_rx_error_o
,
l2p_clk_p_o
=>
gn_l2p_clk_p_o
,
l2p_clk_n_o
=>
gn_l2p_clk_n_o
,
l2p_data_o
=>
gn_l2p_data_o
,
l2p_dframe_o
=>
gn_l2p_dframe_o
,
l2p_valid_o
=>
gn_l2p_valid_o
,
l2p_edb_o
=>
gn_l2p_edb_o
,
l2p_rdy_i
=>
gn_l2p_rdy_i
,
l_wr_rdy_i
=>
gn_l_wr_rdy_i
,
p_rd_d_rdy_i
=>
gn_p_rd_d_rdy_i
,
tx_error_i
=>
gn_tx_error_i
,
vc_rdy_i
=>
gn_vc_rdy_i
,
dma_irq_o
=>
dma_irq
,
irq_p_i
=>
vic_master_irq
,
irq_p_o
=>
gn_gpio_b
(
1
),
wb_master_clk_i
=>
clk_sys_62m5
,
wb_master_rst_n_i
=>
rst_sys_62m5_n
,
wb_master_i
=>
cnx_master_in
(
c_WB_MASTER_GENNUM
),
wb_master_o
=>
cnx_master_out
(
c_WB_MASTER_GENNUM
),
wb_dma_cfg_clk_i
=>
clk_sys_62m5
,
wb_dma_cfg_rst_n_i
=>
rst_sys_62m5_n
,
wb_dma_cfg_i
=>
cnx_slave_in
(
c_WB_SLAVE_DMA
),
wb_dma_cfg_o
=>
cnx_slave_out
(
c_WB_SLAVE_DMA
),
wb_dma_dat_clk_i
=>
clk_sys_62m5
,
wb_dma_dat_rst_n_i
=>
rst_sys_62m5_n
,
wb_dma_dat_i
=>
gn_wb_ddr_in
,
wb_dma_dat_o
=>
gn_wb_ddr_out
);
-- Assign unused outputs
gn_gpio_b
(
0
)
<=
'0'
;
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
gn_rst_n_i
=>
gn_rst_n_i
,
gn_p2l_clk_n_i
=>
gn_p2l_clk_n_i
,
gn_p2l_clk_p_i
=>
gn_p2l_clk_p_i
,
gn_p2l_rdy_o
=>
gn_p2l_rdy_o
,
gn_p2l_dframe_i
=>
gn_p2l_dframe_i
,
gn_p2l_valid_i
=>
gn_p2l_valid_i
,
gn_p2l_data_i
=>
gn_p2l_data_i
,
gn_p_wr_req_i
=>
gn_p_wr_req_i
,
gn_p_wr_rdy_o
=>
gn_p_wr_rdy_o
,
gn_rx_error_o
=>
gn_rx_error_o
,
gn_l2p_clk_n_o
=>
gn_l2p_clk_n_o
,
gn_l2p_clk_p_o
=>
gn_l2p_clk_p_o
,
gn_l2p_dframe_o
=>
gn_l2p_dframe_o
,
gn_l2p_valid_o
=>
gn_l2p_valid_o
,
gn_l2p_edb_o
=>
gn_l2p_edb_o
,
gn_l2p_data_o
=>
gn_l2p_data_o
,
gn_l2p_rdy_i
=>
gn_l2p_rdy_i
,
gn_l_wr_rdy_i
=>
gn_l_wr_rdy_i
,
gn_p_rd_d_rdy_i
=>
gn_p_rd_d_rdy_i
,
gn_tx_error_i
=>
gn_tx_error_i
,
gn_vc_rdy_i
=>
gn_vc_rdy_i
,
gn_gpio_b
=>
gn_gpio_b
,
fmc0_scl_b
=>
fmc0_scl_b
,
fmc0_sda_b
=>
fmc0_sda_b
,
fmc0_prsnt_m2c_n_i
=>
fmc0_prsnt_m2c_n_i
,
onewire_b
=>
carrier_onewire_b
,
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
pcbrev_i
=>
pcbrev_i
,
led_act_o
=>
led_sfp_red_o
,
led_link_o
=>
led_sfp_green_o
,
button1_i
=>
button1_n_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtp_n_i
,
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
plldac_sclk_o
=>
plldac_sclk_o
,
plldac_din_o
=>
plldac_din_o
,
pll25dac_cs_n_o
=>
pll25dac_sync_n_o
,
pll20dac_cs_n_o
=>
pll20dac_sync_n_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_rxn_i
=>
sfp_rxn_i
,
sfp_mod_def0_i
=>
sfp_mod_def0_i
,
sfp_mod_def1_b
=>
sfp_mod_def1_b
,
sfp_mod_def2_b
=>
sfp_mod_def2_b
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
ddr_a_o
=>
ddr0_a_o
,
ddr_ba_o
=>
ddr0_ba_o
,
ddr_cas_n_o
=>
ddr0_cas_n_o
,
ddr_ck_n_o
=>
ddr0_ck_n_o
,
ddr_ck_p_o
=>
ddr0_ck_p_o
,
ddr_cke_o
=>
ddr0_cke_o
,
ddr_dq_b
=>
ddr0_dq_b
,
ddr_ldm_o
=>
ddr0_ldm_o
,
ddr_ldqs_n_b
=>
ddr0_ldqs_n_b
,
ddr_ldqs_p_b
=>
ddr0_ldqs_p_b
,
ddr_odt_o
=>
ddr0_odt_o
,
ddr_ras_n_o
=>
ddr0_ras_n_o
,
ddr_reset_n_o
=>
ddr0_reset_n_o
,
ddr_rzq_b
=>
ddr0_rzq_b
,
ddr_udm_o
=>
ddr0_udm_o
,
ddr_udqs_n_b
=>
ddr0_udqs_n_b
,
ddr_udqs_p_b
=>
ddr0_udqs_p_b
,
ddr_we_n_o
=>
ddr0_we_n_o
,
ddr_dma_clk_i
=>
clk_ref_125m
,
ddr_dma_rst_n_i
=>
rst_ref_125m_n
,
ddr_dma_wb_i
=>
fmc0_wb_ddr_out
,
ddr_dma_wb_o
=>
fmc0_wb_ddr_in
,
ddr_wr_fifo_empty_o
=>
ddr0_wr_fifo_empty
,
clk_sys_62m5_o
=>
clk_sys_62m5
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n
,
clk_ref_125m_o
=>
clk_ref_125m
,
rst_ref_125m_n_o
=>
rst_ref_125m_n
,
irq_user_i
=>
irq_vector
,
wrf_src_o
=>
eth_rx_in
,
wrf_src_i
=>
eth_rx_out
,
wrf_snk_o
=>
eth_tx_in
,
wrf_snk_i
=>
eth_tx_out
,
tm_link_up_o
=>
tm_link_up
,
tm_time_valid_o
=>
tm_time_valid
,
tm_tai_o
=>
tm_tai
,
tm_cycles_o
=>
tm_cycles
,
pps_p_o
=>
open
,
pps_led_o
=>
pps_led
,
link_ok_o
=>
wrabbit_en
,
app_wb_o
=>
cnx_master_out
(
c_WB_MASTER_GENNUM
),
app_wb_i
=>
cnx_master_in
(
c_WB_MASTER_GENNUM
));
------------------------------------------------------------------------------
-- Primary wishbone crossbar
...
...
@@ -678,29 +511,6 @@ begin -- architecture arch
master_i
=>
cnx_slave_out
,
master_o
=>
cnx_slave_in
);
-----------------------------------------------------------------------------
-- Vectored Interrupt Controller (WB Slave)
-----------------------------------------------------------------------------
cmp_vic
:
xwb_vic
generic
map
(
g_INTERFACE_MODE
=>
PIPELINED
,
g_ADDRESS_GRANULARITY
=>
BYTE
,
g_NUM_INTERRUPTS
=>
6
,
g_INIT_VECTORS
=>
c_VIC_VECTOR_TABLE
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
slave_i
=>
cnx_slave_in
(
c_WB_SLAVE_VIC
),
slave_o
=>
cnx_slave_out
(
c_WB_SLAVE_VIC
),
irqs_i
(
0
)
=>
fmc_host_irq
(
0
),
irqs_i
(
1
)
=>
dma_eic_irq
,
irqs_i
(
2
)
=>
mt_hmq_in_irq
,
irqs_i
(
3
)
=>
mt_hmq_out_irq
,
irqs_i
(
4
)
=>
mt_console_irq
,
irqs_i
(
5
)
=>
mt_notify_irq
,
irq_master_o
=>
vic_master_irq
);
-----------------------------------------------------------------------------
-- Mock Turtle (WB Slave)
-----------------------------------------------------------------------------
...
...
@@ -723,17 +533,16 @@ begin -- architecture arch
host_slave_o
=>
cnx_slave_out
(
c_WB_SLAVE_MT
),
clk_ref_i
=>
clk_ref_125m
,
tm_i
=>
tm
,
hmq_in_irq_o
=>
mt_hmq_in_irq
,
hmq_out_irq_o
=>
mt_hmq_out_irq
,
notify_irq_o
=>
mt_notify_irq
,
console_irq_o
=>
mt_console_irq
);
tm
.
cycles
<=
tm_cycles
;
tm
.
tai
<=
tm_tai
;
tm
.
time_valid
<=
tm_time_valid
;
tm
.
link_up
<=
tm_link_up
;
tm
.
aux_locked
(
1
downto
0
)
<=
tm_clk_aux_locked
;
tm
.
aux_locked
(
7
downto
2
)
<=
(
others
=>
'0'
);
hmq_in_irq_o
=>
irq_vector
(
1
),
hmq_out_irq_o
=>
irq_vector
(
2
),
notify_irq_o
=>
irq_vector
(
4
),
console_irq_o
=>
irq_vector
(
3
));
tm
.
cycles
<=
tm_cycles
;
tm
.
tai
<=
tm_tai
;
tm
.
time_valid
<=
tm_time_valid
;
tm
.
link_up
<=
tm_link_up
;
tm
.
aux_locked
<=
(
others
=>
'0'
);
cmp_eth_endpoint
:
entity
work
.
mt_ep_ethernet_single
port
map
(
...
...
@@ -772,131 +581,6 @@ begin -- architecture arch
end
process
p_rmq_assign
;
-----------------------------------------------------------------------------
-- The WR PTP core SVEC board package (WB Slave)
-----------------------------------------------------------------------------
cmp_xwrc_board_spec
:
xwrc_board_spec
generic
map
(
g_SIMULATION
=>
g_SIMULATION
,
g_VERBOSE
=>
FALSE
,
g_WITH_EXTERNAL_CLOCK_INPUT
=>
FALSE
,
g_DPRAM_INITF
=>
g_WRPC_INITF
,
g_AUX_PLL_CFG
=>
c_WRPC_PLL_CONFIG
,
g_FABRIC_IFACE
=>
PLAIN
)
port
map
(
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtp_n_i
,
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
areset_n_i
=>
button1_n_i
,
areset_edge_n_i
=>
gn_rst_n_i
,
clk_sys_62m5_o
=>
clk_sys_62m5
,
clk_ref_125m_o
=>
clk_ref_125m
,
clk_pll_aux_o
=>
clk_pll_aux
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n
,
rst_ref_125m_n_o
=>
rst_ref_125m_n
,
rst_pll_aux_n_o
=>
rst_pll_aux_n
,
plldac_sclk_o
=>
plldac_sclk_o
,
plldac_din_o
=>
plldac_din_o
,
pll25dac_cs_n_o
=>
pll25dac_sync_n_o
,
pll20dac_cs_n_o
=>
pll20dac_sync_n_o
,
sfp_txp_o
=>
sfp_txp_o
,
sfp_txn_o
=>
sfp_txn_o
,
sfp_rxp_i
=>
sfp_rxp_i
,
sfp_rxn_i
=>
sfp_rxn_i
,
sfp_det_i
=>
sfp_mod_def0_i
,
sfp_sda_i
=>
sfp_sda_in
,
sfp_sda_o
=>
sfp_sda_out
,
sfp_scl_i
=>
sfp_scl_in
,
sfp_scl_o
=>
sfp_scl_out
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
onewire_i
=>
onewire_data
,
onewire_oen_o
=>
onewire_oe
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
flash_sclk_o
=>
spi_sclk_o
,
flash_ncs_o
=>
spi_ncs_o
,
flash_mosi_o
=>
spi_mosi_o
,
flash_miso_i
=>
spi_miso_i
,
wb_slave_o
=>
cnx_slave_out
(
c_WB_SLAVE_WRC
),
wb_slave_i
=>
cnx_slave_in
(
c_WB_SLAVE_WRC
),
wrf_src_o
=>
eth_rx_in
,
wrf_src_i
=>
eth_rx_out
,
wrf_snk_o
=>
eth_tx_in
,
wrf_snk_i
=>
eth_tx_out
,
tm_link_up_o
=>
tm_link_up
,
tm_time_valid_o
=>
tm_time_valid
,
tm_tai_o
=>
tm_tai
,
tm_cycles_o
=>
tm_cycles
,
pps_p_o
=>
open
,
pps_led_o
=>
pps_led
,
led_link_o
=>
wr_led_link
,
led_act_o
=>
wr_led_act
,
link_ok_o
=>
wrabbit_en
);
clk_ddr_333m
<=
clk_pll_aux
(
0
);
rst_ddr_333m_n
<=
rst_pll_aux_n
(
0
);
-- Tristates for SFP EEPROM
sfp_mod_def1_b
<=
'0'
when
sfp_scl_out
=
'0'
else
'Z'
;
sfp_mod_def2_b
<=
'0'
when
sfp_sda_out
=
'0'
else
'Z'
;
sfp_scl_in
<=
sfp_mod_def1_b
;
sfp_sda_in
<=
sfp_mod_def2_b
;
-- Tristates for Carrier OneWire
carrier_onewire_b
<=
'0'
when
onewire_oe
=
'1'
else
'Z'
;
onewire_data
<=
carrier_onewire_b
;
------------------------------------------------------------------------------
-- GN4124 DMA interrupt controller
------------------------------------------------------------------------------
gen_dma_irq
:
for
I
in
0
to
1
generate
cmp_dma_irq_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
'1'
,
data_i
=>
dma_irq
(
I
),
synced_o
=>
dma_irq_sync
(
I
));
end
generate
gen_dma_irq
;
cmp_dma_eic
:
entity
work
.
dma_eic
port
map
(
rst_n_i
=>
rst_sys_62m5_n
,
clk_sys_i
=>
clk_sys_62m5
,
wb_adr_i
=>
cnx_slave_in
(
c_WB_SLAVE_DMA_EIC
)
.
adr
(
3
downto
2
),
-- cnx_slave_in.adr is byte address
wb_dat_i
=>
cnx_slave_in
(
c_WB_SLAVE_DMA_EIC
)
.
dat
,
wb_dat_o
=>
cnx_slave_out
(
c_WB_SLAVE_DMA_EIC
)
.
dat
,
wb_cyc_i
=>
cnx_slave_in
(
c_WB_SLAVE_DMA_EIC
)
.
cyc
,
wb_sel_i
=>
cnx_slave_in
(
c_WB_SLAVE_DMA_EIC
)
.
sel
,
wb_stb_i
=>
cnx_slave_in
(
c_WB_SLAVE_DMA_EIC
)
.
stb
,
wb_we_i
=>
cnx_slave_in
(
c_WB_SLAVE_DMA_EIC
)
.
we
,
wb_ack_o
=>
cnx_slave_out
(
c_WB_SLAVE_DMA_EIC
)
.
ack
,
wb_stall_o
=>
cnx_slave_out
(
c_WB_SLAVE_DMA_EIC
)
.
stall
,
wb_int_o
=>
dma_eic_irq
,
irq_dma_done_i
=>
dma_irq_sync
(
0
),
irq_dma_error_i
=>
dma_irq_sync
(
1
)
);
-- Unused wishbone signals
cnx_slave_out
(
c_WB_SLAVE_DMA_EIC
)
.
err
<=
'0'
;
cnx_slave_out
(
c_WB_SLAVE_DMA_EIC
)
.
rty
<=
'0'
;
cmp_fmc0_irq_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
'1'
,
data_i
=>
fmc0_irq
,
synced_o
=>
fmc_host_irq
(
0
));
------------------------------------------------------------------------------
-- FMC ADC mezzanines (wb bridge with cross-clocking)
-- Mezzanine system managment I2C master
...
...
@@ -917,13 +601,6 @@ begin -- architecture arch
master_i
=>
cnx_fmc0_sync_master_in
,
master_o
=>
cnx_fmc0_sync_master_out
);
cmp0_fmc_ddr_wr_fifo_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_125m
,
rst_n_i
=>
'1'
,
data_i
=>
ddr0_wr_fifo_empty
,
synced_o
=>
ddr0_wr_fifo_empty_sync
);
cmp0_tm_time_valid_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_125m
,
...
...
@@ -931,9 +608,16 @@ begin -- architecture arch
data_i
=>
tm_time_valid
,
synced_o
=>
tm_time_valid_sync
);
cmp0_fmc_irq_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
'1'
,
data_i
=>
fmc0_irq
,
synced_o
=>
irq_vector
(
0
));
cmp0_fmc_adc_mezzanine
:
entity
work
.
fmc_adc_mezzanine
generic
map
(
g_MULTISHOT_RAM_SIZE
=>
g_FMC0_MULTISHOT_RAM_SIZE
,
g_MULTISHOT_RAM_SIZE
=>
2048
,
g_SPARTAN6_USE_PLL
=>
FALSE
,
g_TRIG_DELAY_EXT
=>
7
,
g_TRIG_DELAY_SW
=>
10
,
...
...
@@ -952,7 +636,7 @@ begin -- architecture arch
wb_ddr_master_i
=>
fmc0_wb_ddr_in
,
wb_ddr_master_o
=>
fmc0_wb_ddr_out
,
ddr_wr_fifo_empty_i
=>
ddr0_wr_fifo_empty
_sync
,
ddr_wr_fifo_empty_i
=>
ddr0_wr_fifo_empty
,
trig_irq_o
=>
open
,
acq_end_irq_o
=>
open
,
eic_irq_o
=>
fmc0_irq
,
...
...
@@ -1007,112 +691,6 @@ begin -- architecture arch
wr_tm_cycles_i
=>
tm_cycles
,
wr_enable_i
=>
wrabbit_en
);
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr0_ctrl_bank
:
ddr3_ctrl
generic
map
(
g_RST_ACT_LOW
=>
0
,
-- active high reset (simpler internal logic)
g_BANK_PORT_SELECT
=>
"SPEC_BANK3_64B_32B"
,
g_MEMCLK_PERIOD
=>
3000
,
g_SIMULATION
=>
c_FMC0_SIMULATION_STR
,
g_CALIB_SOFT_IP
=>
g_FMC0_CALIB_SOFT_IP
,
g_P0_MASK_SIZE
=>
8
,
g_P0_DATA_PORT_SIZE
=>
64
,
g_P0_BYTE_ADDR_WIDTH
=>
30
,
g_P1_MASK_SIZE
=>
4
,
g_P1_DATA_PORT_SIZE
=>
32
,
g_P1_BYTE_ADDR_WIDTH
=>
30
)
port
map
(
clk_i
=>
clk_ddr_333m
,
rst_n_i
=>
ddr0_rst
,
status_o
=>
ddr0_status
,
ddr3_dq_b
=>
ddr0_dq_b
,
ddr3_a_o
=>
ddr0_a_o
,
ddr3_ba_o
=>
ddr0_ba_o
,
ddr3_ras_n_o
=>
ddr0_ras_n_o
,
ddr3_cas_n_o
=>
ddr0_cas_n_o
,
ddr3_we_n_o
=>
ddr0_we_n_o
,
ddr3_odt_o
=>
ddr0_odt_o
,
ddr3_rst_n_o
=>
ddr0_reset_n_o
,
ddr3_cke_o
=>
ddr0_cke_o
,
ddr3_dm_o
=>
ddr0_ldm_o
,
ddr3_udm_o
=>
ddr0_udm_o
,
ddr3_dqs_p_b
=>
ddr0_ldqs_p_b
,
ddr3_dqs_n_b
=>
ddr0_ldqs_n_b
,
ddr3_udqs_p_b
=>
ddr0_udqs_p_b
,
ddr3_udqs_n_b
=>
ddr0_udqs_n_b
,
ddr3_clk_p_o
=>
ddr0_ck_p_o
,
ddr3_clk_n_o
=>
ddr0_ck_n_o
,
ddr3_rzq_b
=>
ddr0_rzq_b
,
wb0_rst_n_i
=>
fmc_rst_ref_125m_n
,
wb0_clk_i
=>
clk_ref_125m
,
wb0_sel_i
=>
fmc0_wb_ddr_out
.
sel
,
wb0_cyc_i
=>
fmc0_wb_ddr_out
.
cyc
,
wb0_stb_i
=>
fmc0_wb_ddr_out
.
stb
,
wb0_we_i
=>
fmc0_wb_ddr_out
.
we
,
wb0_addr_i
=>
fmc0_wb_ddr_out
.
adr
,
wb0_data_i
=>
fmc0_wb_ddr_out
.
dat
,
wb0_data_o
=>
fmc0_wb_ddr_in
.
dat
,
wb0_ack_o
=>
fmc0_wb_ddr_in
.
ack
,
wb0_stall_o
=>
fmc0_wb_ddr_in
.
stall
,
p0_cmd_empty_o
=>
open
,
p0_cmd_full_o
=>
open
,
p0_rd_full_o
=>
open
,
p0_rd_empty_o
=>
open
,
p0_rd_count_o
=>
open
,
p0_rd_overflow_o
=>
open
,
p0_rd_error_o
=>
open
,
p0_wr_full_o
=>
open
,
p0_wr_empty_o
=>
ddr0_wr_fifo_empty
,
p0_wr_count_o
=>
open
,
p0_wr_underrun_o
=>
open
,
p0_wr_error_o
=>
open
,
wb1_rst_n_i
=>
rst_sys_62m5_n
,
wb1_clk_i
=>
clk_sys_62m5
,
wb1_sel_i
=>
gn_wb_ddr_out
.
sel
,
wb1_cyc_i
=>
gn_wb_ddr_out
.
cyc
,
wb1_stb_i
=>
gn_wb_ddr_out
.
stb
,
wb1_we_i
=>
gn_wb_ddr_out
.
we
,
wb1_addr_i
=>
gn_wb_ddr_out
.
adr
,
wb1_data_i
=>
gn_wb_ddr_out
.
dat
,
wb1_data_o
=>
gn_wb_ddr_in
.
dat
,
wb1_ack_o
=>
gn_wb_ddr_in
.
ack
,
wb1_stall_o
=>
gn_wb_ddr_in
.
stall
,
p1_cmd_empty_o
=>
open
,
p1_cmd_full_o
=>
open
,
p1_rd_full_o
=>
open
,
p1_rd_empty_o
=>
open
,
p1_rd_count_o
=>
open
,
p1_rd_overflow_o
=>
open
,
p1_rd_error_o
=>
open
,
p1_wr_full_o
=>
open
,
p1_wr_empty_o
=>
open
,
p1_wr_count_o
=>
open
,
p1_wr_underrun_o
=>
open
,
p1_wr_error_o
=>
open
);
fmc0_wb_ddr_in
.
err
<=
'0'
;
fmc0_wb_ddr_in
.
rty
<=
'0'
;
cmp_ddr0_calib_done_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
'1'
,
data_i
=>
ddr0_status
(
0
),
synced_o
=>
ddr0_calib_done
);
-- unused Wishbone signals
gn_wb_ddr_in
.
err
<=
'0'
;
gn_wb_ddr_in
.
rty
<=
'0'
;
-- Note: g_address/g_mask index direction is to, master_i/master_o is downto
cpu0_crossbar
:
xwb_crossbar
generic
map
(
...
...
@@ -1153,8 +731,4 @@ begin -- architecture arch
aux_leds_o
(
2
)
<=
not
tm_time_valid
;
aux_leds_o
(
3
)
<=
not
pps_led
;
-- SPEC front panel leds
led_sfp_red_o
<=
led_red
or
wr_led_act
;
led_sfp_green_o
<=
led_green
or
wr_led_link
;
end
architecture
arch
;
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