Commit 5f6b23a1 authored by Dimitris Lampridis's avatar Dimitris Lampridis

tools: move wrtd_builder out of the way and mark it as WIP

parent 90d51cfa
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "spec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx100t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_adc_top"
syn_project = "spec_adc.xise"
syn_tool = "ise"
fetchto = "../../../../dependencies"
ctrls = ["bank3_64b_32b"]
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files = [
"spec_adc.ucf",
]
modules = {
"local" : [
"../../top/spec_adc",
],
}
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# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_fd_tdc_top"
syn_project = "svec_fd_tdc.xise"
syn_tool = "ise"
fetchto = "../../../../dependencies"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files = [
"svec_fd_tdc.ucf",
]
modules = {
"local" : [
"../../top/svec_fd_tdc",
],
}
This diff is collapsed.
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_tdc_fd_top"
syn_project = "svec_tdc_fd.xise"
syn_tool = "ise"
fetchto = "../../../../dependencies"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files = [
"svec_tdc_fd.ucf",
]
modules = {
"local" : [
"../../top/svec_tdc_fd",
],
}
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files = [
"spec_adc_top.vhd",
"../../../spec-lib/carrier_csr_wbgen2_pkg.vhd",
"../../../spec-lib/carrier_csr.vhd",
"../../../spec-lib/dma_eic.vhd",
]
fetchto = "../../../../dependencies"
modules = {
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
"git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git",
],
}
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files = [
"svec_adc_top.vhd",
]
fetchto = "../../../../dependencies"
modules = {
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
"git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git",
],
}
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files = [
"svec_fd_tdc_top.vhd",
]
fetchto = "../../../../dependencies"
modules = {
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git",
"git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git",
],
}
This diff is collapsed.
files = [
"svec_tdc_fd_top.vhd",
]
fetchto = "../../../../dependencies"
modules = {
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
"git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git",
"git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git",
],
}
This diff is collapsed.
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project save
xilinx::project close
This is a work-in-progress effort to implement a WRTD HDL generator that can take as input a
YAML-based description of a WRTD node (made of supported hardware, such as the SPEC, SVEC, FMC-ADC,
etc) and generate the top-level VHDL and necessary infrastructure to synthesize it.
**This tool is not yet done!**
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