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White Rabbit Trigger Distribution
Commit 60bcd7da authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: work in progress to update the SVEC TDC+FD reference design

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mock-turtle @ 59a2c707
Subproject commit f30132905e64f360372278fee7f07c60f60b97e6 Subproject commit 59a2c707c28ea99ee15a17eb1f1c903f6644c7b1
hdl/syn/wrtd_ref_svec_tdc_fd/syn_extra_steps.tcl
View file @ 60bcd7da
...@@ -14,13 +14,19 @@ xilinx::project open $project_file ...@@ -14,13 +14,19 @@ xilinx::project open $project_file
# Not respected by ISE when passed through hdlmake: # Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs # 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map # 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map" xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route" xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes" xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes" xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On" xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save xilinx::project save
xilinx::project close xilinx::project close
hdl/testbench/include/wrtd_definitions.svh
View file @ 60bcd7da
...@@ -27,6 +27,8 @@ ...@@ -27,6 +27,8 @@
`ifndef __WRTD_DEFINE_INCLUDED `ifndef __WRTD_DEFINE_INCLUDED
`define __WRTD_DEFINE_INCLUDED `define __WRTD_DEFINE_INCLUDED
`include "simdrv_defs.svh"
`define WRTD_MAX_CPUS 4 `define WRTD_MAX_CPUS 4
`define WRTD_MAX_DEVS 4 `define WRTD_MAX_DEVS 4
......
hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
View file @ 60bcd7da
# HDLMake 'develop' branch required. board = "svec"
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
sim_tool = "modelsim" sim_tool = "modelsim"
sim_top = "main" sim_top = "main"
action = "simulation" action = "simulation"
target = "xilinx" target = "xilinx"
board = "svec"
syn_device = "xc6slx150t" syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh" vcom_opt = "-93 -mixedsvvh"
fetchto="../../../dependencies" fetchto="../../../dependencies"
include_dirs = [ include_dirs = [
fetchto + "/mock-turtle/hdl/testbench/include/", "../include",
fetchto + "/mock-turtle/hdl/testbench/include/regs/",
fetchto + "/general-cores/sim/", fetchto + "/general-cores/sim/",
fetchto + "/urv-core/rtl/", fetchto + "/mock-turtle/hdl/testbench/include/",
] ]
files = [ files = [
"main.sv", "main.sv",
"dut_env.sv",
"synthesis_descriptor.vhd", "synthesis_descriptor.vhd",
] ]
......
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv 0 → 100644
View file @ 60bcd7da
This diff is collapsed.
hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
View file @ 60bcd7da
This diff is collapsed.
hdl/testbench/wrtd_ref_svec_tdc_fd/run.do
View file @ 60bcd7da
vsim -quiet -L unisim work.main -novopt -suppress 8683,8684,8822 vsim -quiet -t 10fs -L unisim work.main
set StdArithNoWarnings 1 set StdArithNoWarnings 1
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
radix -hexadecimal radix -hexadecimal
run 1000us log -r /*
run -all
hdl/testbench/wrtd_ref_svec_tdc_fd/run_ci.do
View file @ 60bcd7da
# Modelsim run script for continuous integration # Modelsim run script for continuous integration
# execute: vsim -c -do "run_ci.do" # execute: vsim -c -do "run_ci.do"
vsim -quiet -L unisim work.main -suppress 8683,8684,8822 vsim -quiet -t 10fs -L unisim work.main
set StdArithNoWarnings 1 set StdArithNoWarnings 1
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
run 1000us run -all
exit exit
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ 60bcd7da
...@@ -236,7 +236,7 @@ architecture arch of wrtd_ref_spec150t_adc is ...@@ -236,7 +236,7 @@ architecture arch of wrtd_ref_spec150t_adc is
constant c_WB_SLAVE_SPEC_CSR : integer := 0; constant c_WB_SLAVE_SPEC_CSR : integer := 0;
constant c_WB_SLAVE_VIC : integer := 1; constant c_WB_SLAVE_VIC : integer := 1;
constant c_WB_SLAVE_BASE : integer := 2; constant c_WB_SLAVE_BASE : integer := 2;
constant c_WB_SLAVE_DMA : integer := c_WB_SLAVE_BASE + 0; constant c_WB_SLAVE_DMA : integer := c_WB_SLAVE_BASE + 0;
constant c_WB_SLAVE_DMA_EIC : integer := c_WB_SLAVE_BASE + 1; constant c_WB_SLAVE_DMA_EIC : integer := c_WB_SLAVE_BASE + 1;
constant c_WB_SLAVE_FMC_ADC : integer := c_WB_SLAVE_BASE + 2; constant c_WB_SLAVE_FMC_ADC : integer := c_WB_SLAVE_BASE + 2;
...@@ -310,14 +310,13 @@ architecture arch of wrtd_ref_spec150t_adc is ...@@ -310,14 +310,13 @@ architecture arch of wrtd_ref_spec150t_adc is
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := ( constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_SPEC_CSR => f_sdb_embed_device(c_WB_SPEC_CSR_SDB, x"00001000"), c_WB_SLAVE_SPEC_CSR => f_sdb_embed_device(c_WB_SPEC_CSR_SDB, x"00001000"),
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00001200"), c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00001200"),
c_WB_SLAVE_DMA => f_sdb_embed_device(c_WB_DMA_CTRL_SDB, x"00002000"), c_WB_SLAVE_DMA => f_sdb_embed_device(c_WB_DMA_CTRL_SDB, x"00002000"),
c_WB_SLAVE_DMA_EIC => f_sdb_embed_device(c_WB_DMA_EIC_SDB, x"00002200"), c_WB_SLAVE_DMA_EIC => f_sdb_embed_device(c_WB_DMA_EIC_SDB, x"00002200"),
c_WB_SLAVE_FMC_ADC => f_sdb_embed_bridge(c_FMC_BRIDGE_SDB, x"00004000"), c_WB_SLAVE_FMC_ADC => f_sdb_embed_bridge(c_FMC_BRIDGE_SDB, x"00004000"),
c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"), c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"),
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"), c_WB_DESC_SYN => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
c_WB_DESC_SYN => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO), c_WB_DESC_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL));
c_WB_DESC_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL));
-- not really used, will be reprogrammed by software -- not really used, will be reprogrammed by software
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 5) := ( constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 5) := (
...@@ -457,8 +456,8 @@ architecture arch of wrtd_ref_spec150t_adc is ...@@ -457,8 +456,8 @@ architecture arch of wrtd_ref_spec150t_adc is
signal eth_rx_in : t_wrf_sink_in; signal eth_rx_in : t_wrf_sink_in;
-- MT Dedicated WB interfaces to FMCs -- MT Dedicated WB interfaces to FMCs
signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to 1 - 1); signal fmc_dp_wb_out : t_wishbone_master_out;
signal fmc_dp_wb_in : t_wishbone_master_in_array(0 to 1 - 1); signal fmc_dp_wb_in : t_wishbone_master_in;
-- WRPC TM interface and aux clocks -- WRPC TM interface and aux clocks
signal tm_link_up : std_logic; signal tm_link_up : std_logic;
...@@ -708,8 +707,8 @@ begin -- architecture arch ...@@ -708,8 +707,8 @@ begin -- architecture arch
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
sp_master_o => open, sp_master_o => open,
sp_master_i => c_DUMMY_WB_MASTER_IN, sp_master_i => c_DUMMY_WB_MASTER_IN,
dp_master_o => fmc_dp_wb_out, dp_master_o(0) => fmc_dp_wb_out,
dp_master_i => fmc_dp_wb_in, dp_master_i(0) => fmc_dp_wb_in,
rmq_endpoint_o => rmq_endpoint_out, rmq_endpoint_o => rmq_endpoint_out,
rmq_endpoint_i => rmq_endpoint_in, rmq_endpoint_i => rmq_endpoint_in,
host_slave_i => cnx_slave_in(c_WB_SLAVE_MT), host_slave_i => cnx_slave_in(c_WB_SLAVE_MT),
...@@ -1120,8 +1119,8 @@ begin -- architecture arch ...@@ -1120,8 +1119,8 @@ begin -- architecture arch
port map ( port map (
clk_sys_i => clk_sys_62m5, clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
slave_i(0) => fmc_dp_wb_out(0), slave_i(0) => fmc_dp_wb_out,
slave_o(0) => fmc_dp_wb_in(0), slave_o(0) => fmc_dp_wb_in,
master_i(1) => wb_adc0_trigout_slave_out, master_i(1) => wb_adc0_trigout_slave_out,
master_i(0) => wb_adc0_trigin_slave_out, master_i(0) => wb_adc0_trigin_slave_out,
master_o(1) => wb_adc0_trigout_slave_in, master_o(1) => wb_adc0_trigout_slave_in,
......
hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
View file @ 60bcd7da
...@@ -52,9 +52,9 @@ use unisim.vcomponents.all; ...@@ -52,9 +52,9 @@ use unisim.vcomponents.all;
entity wrtd_ref_svec_tdc_fd is entity wrtd_ref_svec_tdc_fd is
generic ( generic (
g_WR_DPRAM_INITF : string := "../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram"; g_WRPC_INITF : string := "../../../dependencies/wr-cores/bin/wrpc/wrc_phy8.bram";
g_MT_CPU0_INITF : string := "../../../software/firmware/tdc/wrtd-rt-tdc.bram"; g_MT_CPU0_INITF : string := "../../../software/firmware/tdc/wrtd-rt-tdc.bram";
g_MT_CPU1_INITF : string := "../../../software/firmware/fd/wrtd-rt-fd.bram"; g_MT_CPU1_INITF : string := "../../../software/firmware/fd/wrtd-rt-fd.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the -- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts -- testbench. Its purpose is to reduce some internal counters/timeouts
...@@ -151,7 +151,7 @@ entity wrtd_ref_svec_tdc_fd is ...@@ -151,7 +151,7 @@ entity wrtd_ref_svec_tdc_fd is
-- Onewire interface -- Onewire interface
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
onewire_b : inout std_logic; carrier_onewire_b : inout std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- UART -- UART
...@@ -338,27 +338,27 @@ architecture arch of wrtd_ref_svec_tdc_fd is ...@@ -338,27 +338,27 @@ architecture arch of wrtd_ref_svec_tdc_fd is
constant c_WB_SLAVE_FDL : integer := 2; constant c_WB_SLAVE_FDL : integer := 2;
constant c_WB_SLAVE_MT : integer := 3; constant c_WB_SLAVE_MT : integer := 3;
constant c_WB_SLAVE_WRC : integer := 4; constant c_WB_SLAVE_WRC : integer := 4;
constant c_WB_DESC_SYN : integer := 5; constant c_WB_DESC_SYN : integer := c_NUM_WB_SLAVES;
constant c_WB_DESC_URL : integer := 6; constant c_WB_DESC_URL : integer := c_NUM_WB_SLAVES + 1;
-- sdb header address on primary crossbar -- sdb header address on primary crossbar
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000"; constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- f_xwb_bridge_manual_sdb(size, sdb_addr) -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address -- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_wrc_bridge_sdb : t_sdb_bridge := constant c_WRC_BRIDGE_SDB : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000"); f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_tdc_bridge_sdb : t_sdb_bridge := constant c_TDC_BRIDGE_SDB : t_sdb_bridge :=
f_xwb_bridge_manual_sdb(x"00007FFF", x"00000000"); f_xwb_bridge_manual_sdb(x"00007FFF", x"00000000");
-- Primary wishbone crossbar layout -- Primary wishbone crossbar layout
constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := ( constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES + 1 downto 0) := (
c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00002000"), c_WB_SLAVE_VIC => f_sdb_embed_device(c_XWB_VIC_SDB, x"00002000"),
c_WB_SLAVE_TDC => f_sdb_embed_bridge(c_tdc_bridge_sdb, x"00010000"), c_WB_SLAVE_TDC => f_sdb_embed_bridge(c_TDC_BRIDGE_SDB, x"00010000"),
c_WB_SLAVE_FDL => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00018000"), c_WB_SLAVE_FDL => f_sdb_embed_device(c_FD_SDB_DEVICE, x"00018000"),
c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"), c_WB_SLAVE_MT => f_sdb_embed_device(c_MOCK_TURTLE_SDB, x"00020000"),
c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00040000"), c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_WRC_BRIDGE_SDB, x"00040000"),
c_WB_DESC_SYN => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO), c_WB_DESC_SYN => f_sdb_embed_synthesis(c_SDB_SYNTHESIS_INFO),
c_WB_DESC_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL)); c_WB_DESC_URL => f_sdb_embed_repo_url(c_SDB_REPO_URL));
...@@ -376,7 +376,7 @@ architecture arch of wrtd_ref_svec_tdc_fd is ...@@ -376,7 +376,7 @@ architecture arch of wrtd_ref_svec_tdc_fd is
constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) := constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
(0 => x"10000000"); (0 => x"10000000");
constant c_mt_config : t_mt_config := constant c_MT_CONFIG : t_mt_config :=
( (
app_id => x"115790de", app_id => x"115790de",
cpu_count => 2, cpu_count => 2,
...@@ -384,22 +384,14 @@ architecture arch of wrtd_ref_svec_tdc_fd is ...@@ -384,22 +384,14 @@ architecture arch of wrtd_ref_svec_tdc_fd is
0 | 1 => ( 0 | 1 => (
memsize => 8192, memsize => 8192,
hmq_config => ( hmq_config => (
slot_count => 2, slot_count => 1,
slot_config => ( slot_config => (
0 => ( 0 => (
-- Control entries_bits => 4,
entries_bits => 3,
width_bits => 7, width_bits => 7,
header_bits => 2, header_bits => 2,
endpoint_id => x"0000_0000", endpoint_id => x"0000_0000",
enable_config_space => FALSE), enable_config_space => FALSE),
1 => (
-- Log
entries_bits => 7,
width_bits => 4,
header_bits => 2,
endpoint_id => x"0000_0000",
enable_config_space => FALSE),
others => c_DUMMY_MT_MQUEUE_SLOT)), others => c_DUMMY_MT_MQUEUE_SLOT)),
rmq_config => ( rmq_config => (
slot_count => 1, slot_count => 1,
...@@ -413,7 +405,7 @@ architecture arch of wrtd_ref_svec_tdc_fd is ...@@ -413,7 +405,7 @@ architecture arch of wrtd_ref_svec_tdc_fd is
others => c_DUMMY_MT_MQUEUE_SLOT))), others => c_DUMMY_MT_MQUEUE_SLOT))),
others => ( others => (
0, c_MT_DEFAULT_MQUEUE_CONFIG, c_MT_DEFAULT_MQUEUE_CONFIG)), 0, c_MT_DEFAULT_MQUEUE_CONFIG, c_MT_DEFAULT_MQUEUE_CONFIG)),
shared_mem_size => 1024 shared_mem_size => 256
); );
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -544,7 +536,7 @@ architecture arch of wrtd_ref_svec_tdc_fd is ...@@ -544,7 +536,7 @@ architecture arch of wrtd_ref_svec_tdc_fd is
signal fmc0_scl_out : std_logic; signal fmc0_scl_out : std_logic;
signal fmc0_sda_out : std_logic; signal fmc0_sda_out : std_logic;
attribute iob : string; attribute iob : string;
attribute iob of pps : signal is "FORCE"; attribute iob of pps : signal is "FORCE";
begin -- architecture arch begin -- architecture arch
...@@ -632,7 +624,6 @@ begin -- architecture arch ...@@ -632,7 +624,6 @@ begin -- architecture arch
vme_addr_dir_o <= vme_addr_dir_int; vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int; vme_data_dir_o <= vme_data_dir_int;
end generate gen_with_vme64_core; end generate gen_with_vme64_core;
gen_without_vme64_core : if g_SIM_BYPASS_VME generate gen_without_vme64_core : if g_SIM_BYPASS_VME generate
...@@ -752,9 +743,11 @@ begin -- architecture arch ...@@ -752,9 +743,11 @@ begin -- architecture arch
cmp_xwrc_board_svec : xwrc_board_svec cmp_xwrc_board_svec : xwrc_board_svec
generic map ( generic map (
g_simulation => g_simulation, g_SIMULATION => g_SIMULATION,
g_dpram_initf => g_WR_DPRAM_INITF, g_VERBOSE => FALSE,
g_aux_clks => 2) g_WITH_EXTERNAL_CLOCK_INPUT => TRUE,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 2)
port map ( port map (
clk_20m_vcxo_i => clk_20m_vcxo_i, clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i, clk_125m_pllref_p_i => clk_125m_pllref_p_i,
...@@ -832,8 +825,8 @@ begin -- architecture arch ...@@ -832,8 +825,8 @@ begin -- architecture arch
sfp_sda_in <= sfp_mod_def2_b; sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access -- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z'; carrier_onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b; onewire_data <= carrier_onewire_b;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- FMC TDC (SVEC slot #1) -- FMC TDC (SVEC slot #1)
...@@ -841,8 +834,8 @@ begin -- architecture arch ...@@ -841,8 +834,8 @@ begin -- architecture arch
U_TDC_Core : fmc_tdc_wrapper U_TDC_Core : fmc_tdc_wrapper
generic map ( generic map (
g_simulation => f_int2bool(g_simulation), g_SIMULATION => f_int2bool(g_SIMULATION),
g_with_direct_readout => TRUE) g_WITH_DIRECT_READOUT => TRUE)
port map ( port map (
clk_sys_i => clk_sys_62m5, clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n, rst_sys_n_i => rst_sys_62m5_n,
...@@ -939,10 +932,10 @@ begin -- architecture arch ...@@ -939,10 +932,10 @@ begin -- architecture arch
U_FineDelay_Core : fine_delay_core U_FineDelay_Core : fine_delay_core
generic map ( generic map (
g_with_wr_core => TRUE, g_WITH_WR_CORE => TRUE,
g_simulation => f_int2bool(g_simulation), g_SIMULATION => f_int2bool(g_SIMULATION),
g_interface_mode => PIPELINED, g_INTERFACE_MODE => PIPELINED,
g_address_granularity => BYTE) g_ADDRESS_GRANULARITY => BYTE)
port map ( port map (
clk_ref_0_i => dcm1_clk_ref_0, clk_ref_0_i => dcm1_clk_ref_0,
clk_ref_180_i => dcm1_clk_ref_180, clk_ref_180_i => dcm1_clk_ref_180,
...@@ -1044,10 +1037,10 @@ begin -- architecture arch ...@@ -1044,10 +1037,10 @@ begin -- architecture arch
cmp_led_controller : gc_bicolor_led_ctrl cmp_led_controller : gc_bicolor_led_ctrl
generic map( generic map(
g_nb_column => 4, g_NB_COLUMN => 4,
g_nb_line => 2, g_NB_LINE => 2,
g_clk_freq => 62500000, -- in Hz g_CLK_FREQ => 62500000, -- in Hz
g_refresh_rate => 250 -- in Hz g_REFRESH_RATE => 250 -- in Hz
) )
port map( port map(
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
...@@ -1062,21 +1055,21 @@ begin -- architecture arch ...@@ -1062,21 +1055,21 @@ begin -- architecture arch
line_oen_o => fp_led_line_oen_o); line_oen_o => fp_led_line_oen_o);
-- LED 1 -- LED 1
svec_led(1 downto 0) <= c_led_green when wr_led_link = '1' else c_led_red; svec_led(1 downto 0) <= c_LED_GREEN when wr_led_link = '1' else c_LED_RED;
-- LED 2 -- LED 2
svec_led(3 downto 2) <= c_led_green when tm_clk_aux_locked(0) = '1' else c_led_red; svec_led(3 downto 2) <= c_LED_GREEN when tm_clk_aux_locked(0) = '1' else c_LED_RED;
-- LED 3 -- LED 3
svec_led(5 downto 4) <= c_led_green when tm_time_valid = '1' else c_led_red; svec_led(5 downto 4) <= c_LED_GREEN when tm_time_valid = '1' else c_LED_RED;
-- LED 4 -- LED 4
svec_led(7 downto 6) <= c_led_red_green when vme_access_led = '1' else c_led_off; svec_led(7 downto 6) <= c_LED_RED_GREEN when vme_access_led = '1' else c_LED_OFF;
-- LED 5 -- LED 5
svec_led(9 downto 8) <= c_led_red_green when wr_led_act = '1' else c_led_off; svec_led(9 downto 8) <= c_LED_RED_GREEN when wr_led_act = '1' else c_LED_OFF;
-- LED 6 -- LED 6
svec_led(11 downto 10) <= c_led_green when tm_clk_aux_locked(1) = '1' else c_led_red; svec_led(11 downto 10) <= c_LED_GREEN when tm_clk_aux_locked(1) = '1' else c_LED_RED;
-- LED 7 -- LED 7
svec_led(13 downto 12) <= c_led_off; svec_led(13 downto 12) <= c_LED_OFF;
-- LED 8 -- LED 8
svec_led(15 downto 14) <= c_led_green when pps_led = '1' else c_led_off; svec_led(15 downto 14) <= c_LED_GREEN when pps_led = '1' else c_LED_OFF;
-- Div by 2 reference clock to LEMO connector -- Div by 2 reference clock to LEMO connector
process(clk_ref_125m) process(clk_ref_125m)
......
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