[hdl] convert WRTD SVEC TDC-FD reference node to the Convention (synthesized,…

[hdl] convert WRTD SVEC TDC-FD reference node to the Convention (synthesized, not tested, fails timing)

[hdl] convert WRTD SVEC TDC-FD reference node to the Convention (synthesized,…
[hdl] convert WRTD SVEC TDC-FD reference node to the Convention (synthesized, not tested, fails timing)
6118f656 · Dimitris Lampridis · fb152b67 · 6118f656 · 1a129390 · 5dde6da5
Commit 6118f656 authored Jul 25, 2019 by Dimitris Lampridis
15 changed files
--- a/.gitmodules
+++ b/.gitmodules
@@ -31,3 +31,6 @@
 [submodule "dependencies/spec"]
 	path = dependencies/spec
 	url = https://ohwr.org/project/spec.git
+[submodule "dependencies/svec"]
+	path = dependencies/svec
+	url = https://ohwr.org/project/svec.git
--- a/ddr3-sp6-core @ 1a129390
+++ b/ddr3-sp6-core @ 1a129390
-Subproject commit bb5b8f75e6f85335b43fef320375404686a74008
+Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
--- a/general-cores @ 5dde6da5
+++ b/general-cores @ 5dde6da5
-Subproject commit ac43a1dbde29bcbd9126d877477e77b620176bac
+Subproject commit 5dde6da558083312cfd98d721e14b36a03e2a0bc
--- a/svec @ 41b383af
+++ b/svec @ 41b383af
+Subproject commit 41b383af43d4ea5f8cc7e90555d78f41227dd0b2
--- a/vme64x-core @ 366ca4db
+++ b/vme64x-core @ 366ca4db
-Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
+Subproject commit 366ca4dbe1777f5bc98341d2878070a6c6fa350f
--- a/hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
-# HDLMake 'develop' branch required.
-#
-# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
-# branch of hdlmake, commit db4e1ab.
 board  = "svec"
 target = "xilinx"
 action = "synthesis"
@@ -14,19 +9,14 @@ syn_top     = "wrtd_ref_svec_tdc_fd"
 syn_project = "wrtd_ref_svec_tdc_fd.xise"
 syn_tool    = "ise"
-fetchto = "../../../dependencies"
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
-syn_pre_project_cmd = "make -C ../../../software/firmware"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../../dependencies"
-syn_post_project_cmd = (
-    "$(TCL_INTERPRETER) " + \
-    fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
-    syn_tool + " $(PROJECT_FILE);" \
-    "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
-)
 files = [
    "wrtd_ref_svec_tdc_fd.ucf",
+    "buildinfo_pkg.vhd",
 ]
 modules = {
@@ -34,3 +24,17 @@ modules = {
        "../../top/wrtd_ref_svec_tdc_fd",
    ],
 }
+syn_pre_project_cmd = "make -C ../../../software/firmware"
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
+syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
+svec_template_ucf = ['wr', 'led', 'gpio']
+ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
--- a/hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
+++ b/hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
--- a/hdl/testbench/wrtd_ref_spec150t_adc/buildinfo_pkg.vhd
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/buildinfo_pkg.vhd
-- Buildinfo for project blah
--
-- This file was automatically generated; do not edit
-package buildinfo_pkg is
-  constant buildinfo : string :=
-       "buildinfo:1" & LF
-     & "module:wrtd_ref_spec150t_adc" & LF
-     & "commit:cb32df93f503c2ec56ef759ec063dd8557848e2b" & LF
-     & "syntool:modelsim" & LF
-     & "syndate:Wednesday, July 17 2019" & LF
-     & "synauth:Dimitris Lampridis" & LF;
-end buildinfo_pkg;
--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/.gitignore
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/.gitignore
@@ -3,3 +3,4 @@ Makefile
 modelsim.ini
 transcript*
 *.wlf
+buildinfo_pkg.vhd
--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
@@ -6,7 +6,10 @@ target     = "xilinx"
 syn_device = "xc6slx150t"
 vcom_opt   = "-93 -mixedsvvh"
-fetchto="../../../dependencies"
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../../dependencies"
 sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"
@@ -14,12 +17,13 @@ include_dirs = [
    "../include",
    fetchto + "/general-cores/sim/",
    fetchto + "/mock-turtle/hdl/testbench/include/",
+    fetchto + "/vme64x-core/hdl/sim/vme64x_bfm/",
 ]
 files = [
    "main.sv",
    "dut_env.sv",
-    "synthesis_descriptor.vhd",
+    "buildinfo_pkg.vhd",
 ]
 modules = {
@@ -27,3 +31,13 @@ modules = {
        "../../top/wrtd_ref_svec_tdc_fd",
    ],
 }
+ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
+svec_template_ucf = []
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
@@ -25,7 +25,8 @@
 `timescale 1ns/1ps
-`include "vhd_wishbone_master.svh"
+`include "vme64x_bfm.svh"
+`include "svec_vme_buffers.svh"
 module simple_tdc_driver
  (
@@ -211,7 +212,7 @@ endmodule // simple_fdelay_mon
 module dut_env
  (
-   IVHDWishboneMaster host,
+   IVME64X VME,
   output clk_sys, rst_sys_n,
          sfp_txp_o, sfp_txn_o,
   input  sfp_rxp_i, sfp_rxn_i
@@ -247,24 +248,47 @@ module dut_env
   // The DUT
   //---------------------------------------------------------------------------
+   `DECLARE_VME_BUFFERS(VME.slave);
+   bit [4:0] slot_id = 8;
   wrtd_ref_svec_tdc_fd #
     (
      .g_SIMULATION     (1),
-      .g_SIM_BYPASS_VME (1),
      .g_WRPC_INITF     ("../../../dependencies/wr-cores/bin/wrpc/wrc_phy8_sim.bram")
      )
   DUT
     (
      .rst_n_i                    (1'b1),
-      .vme_sysreset_n_i           (1'b1),
+      .vme_sysreset_n_i           (VME_RST_n),
+      .vme_as_n_i                 (VME_AS_n),
+      .vme_write_n_i              (VME_WRITE_n),
+      .vme_am_i                   (VME_AM),
+      .vme_ds_n_i                 (VME_DS_n),
+      .vme_gap_i                  (^slot_id),
+      .vme_ga_i                   (~slot_id),
+      .vme_berr_o                 (VME_BERR),
+      .vme_dtack_n_o              (VME_DTACK_n),
+      .vme_retry_n_o              (VME_RETRY_n),
+      .vme_retry_oe_o             (VME_RETRY_OE),
+      .vme_lword_n_b              (VME_LWORD_n),
+      .vme_addr_b                 (VME_ADDR),
+      .vme_data_b                 (VME_DATA),
+      .vme_irq_o                  (VME_IRQ_n),
+      .vme_iack_n_i               (VME_IACK_n),
+      .vme_iackin_n_i             (VME_IACKIN_n),
+      .vme_iackout_n_o            (VME_IACKOUT_n),
+      .vme_dtack_oe_o             (VME_DTACK_OE),
+      .vme_data_dir_o             (VME_DATA_DIR),
+      .vme_data_oe_n_o            (VME_DATA_OE_N),
+      .vme_addr_dir_o             (VME_ADDR_DIR),
+      .vme_addr_oe_n_o            (VME_ADDR_OE_N),
      .clk_125m_pllref_p_i        (clk_125m_pll),
      .clk_125m_pllref_n_i        (~clk_125m_pll),
      .clk_125m_gtp_p_i           (clk_125m_gtp),
      .clk_125m_gtp_n_i           (~clk_125m_gtp),
      .clk_20m_vcxo_i             (clk_20m_vcxo),
-      .sim_wb_i                   (host.out),
+      .onewire_b                  (),
-      .sim_wb_o                   (host.in),
-      .carrier_onewire_b          (),
      .sfp_txp_o                  (sfp_txp_o),
      .sfp_txn_o                  (sfp_txn_o),
      .sfp_rxp_i                  (sfp_rxp_i),
@@ -363,7 +387,7 @@ module dut_env
   initial begin
      //  No pulse before: WR (300us) + TDC setup.
-      automatic time start = 480us;
+      automatic time start = 850us;
      push_pulse(0, start + 10us);
      push_pulse(1, start + 30us);
@@ -376,16 +400,16 @@ module dut_env
   initial begin
      // Skip WR SoftPLL lock
-      force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
+      force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
        WRPC.U_SOFTPLL.U_Wrapped_Softpll.out_locked_o = 3'b111;
      // Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
-      force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
+      force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D1.OPMODE_dly = 0;
-      force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
+      force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D2.OPMODE_dly = 0;
-      force DUT.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
+      force DUT.inst_svec_template.gen_wr.cmp_xwrc_board_svec.cmp_board_common.cmp_xwr_core.
        WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
          multiplier.D3.OPMODE_dly = 0;
   end // initial begin

--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/main.sv
@@ -24,10 +24,13 @@
 `timescale 1ns/1ps
+`include "vme64x_bfm.svh"
 `include "wrtd_driver.svh"
-`include "vhd_wishbone_master.svh"
-`define TDC_DIRECT_BASE 'h18000
+`define VME_OFFSET      'h8000_0000
+`define TDC_DIRECT_BASE `VME_OFFSET + 'h0001_8000
+`define MT_BASE         `VME_OFFSET + 'h0002_0000
 module main;
@@ -35,9 +38,9 @@ module main;
   wire sfp_txp, sfp_txn, sfp_rxp, sfp_rxn;
-   IVHDWishboneMaster host (clk_sys, rst_sys_n);
+   IVME64X VME(rst_sys_n);
-   dut_env DUT (host, clk_sys, rst_sys_n, sfp_txp, sfp_txn, sfp_rxp, sfp_rxn);
+   dut_env DUT (VME, clk_sys, rst_sys_n, sfp_txp, sfp_txn, sfp_rxp, sfp_rxn);
   IMockTurtleIRQ MtIrqMonitor (`MT_ATTACH_IRQ(DUT.DUT.cmp_mock_turtle));
@@ -46,18 +49,35 @@ module main;
   WrtdDrv dev;
-   const uint64_t MT_BASE = 'h0002_0000;
+   initial begin
-   CBusAccessor acc;
+      CBusAccessor_VME64x acc;
-   initial begin
+      acc = new(VME.tb);
      $timeformat (-6, 3, "us", 10);
-      #10us;
+      #5us;
-      acc = host.get_accessor();
-      acc.set_default_xfer_size(4);
+      /* map func0 to 0x80000000, A32 */
-      dev = new (acc, MT_BASE, MtIrqMonitor, "DUT");
+      acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
+      acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
+      acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
+      acc.set_default_modifiers(A32 | D32 | SINGLE);
+      /* Hack around CBusAccessor to make it work like CBusAccessor_VME64x. This is needed
+       because WrtdDev expects a CBusAccesor and will not respect the m_default_modifiers value
+       of CBusAccessor_VME64x when performing reads/writes. */
+      acc.set_default_xfer_size(A32 | D32 | SINGLE);
+      acc.write(`TDC_DIRECT_BASE + 'h4, 'h40);
+      #5us;
+      dev = new (acc, `MT_BASE, MtIrqMonitor, "DUT");
      dev.init();
      dev.add_rule ( "rule0" );
@@ -86,8 +106,19 @@ module main;
      // Set dead-time
      acc.write(`TDC_DIRECT_BASE + 'h4, 'h40);
+      #5us;
      // Enable channels
      acc.write(`TDC_DIRECT_BASE + 'h0, 'h1f);
+      // Force start_fpga from TDC to make sure that the FSM has been started
+      force DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga = 'b1;
+      #100ns;
+      release DUT.DUT.U_TDC_Core.cmp_tdc_mezz.cmp_tdc_core.start_from_fpga;
+      dev.mdisplay("Configuration complete, ready to accept pulses...");
   end
   initial begin

--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/synthesis_descriptor.vhd
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/synthesis_descriptor.vhd
--------------------------------------------------------------------------------
-- SDB meta information for svec_list_tdc_fd.xise.
--
-- This file was automatically generated by ../../../ip_cores/general-cores/tools/sdb_desc_gen.tcl on:
-- Friday, July 20 2018
--
-- ../../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki
--
-- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use work.wishbone_pkg.all;
-package synthesis_descriptor is
-  constant c_sdb_synthesis_info : t_sdb_synthesis := (
-    syn_module_name  => "svec_list_tdc_fd",
-    syn_commit_id    => "4a68a12eede44d878435d25c3c7eaaf4",
-    syn_tool_name    => "ISE     ",
-    syn_tool_version => x"00000147",
-    syn_date         => x"20180720",
-    syn_username     => "Dimitris Lampri");
-  constant c_sdb_repo_url : t_sdb_repo_url := (
-    repo_url => "ssh://git@gitlab.cern.ch:7999/coht/wr-trigger-distribution.git ");
-end package synthesis_descriptor;
--- a/hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
@@ -6,6 +6,7 @@ fetchto = "../../../dependencies"
 modules = {
    "git" : [
+        "https://ohwr.org/project/svec.git",
        "https://ohwr.org/project/general-cores.git",
        "https://ohwr.org/project/wr-cores.git",
        "https://ohwr.org/project/vme64x-core.git",
@@ -13,5 +14,6 @@ modules = {
        "https://ohwr.org/project/mock-turtle.git",
        "https://ohwr.org/project/fmc-tdc-1ns-5cha-gw.git",
        "https://ohwr.org/project/fmc-delay-1ns-8cha.git",
+        "https://ohwr.org/project/ddr3-sp6-core.git",
    ],
 }
--- a/hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd
+++ b/hdl/top/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.vhd