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White Rabbit Trigger Distribution
Commit 6d5d6061 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] review SPEC constraints

parent 1037cd98
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hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @ 6d5d6061
#=============================================================================== #===============================================================================
# IO Location Constraints # IO Location Constraints
#=============================================================================== #===============================================================================
#---------------------------------------- #----------------------------------------
# GN4124 interface # GN4124 interface
#---------------------------------------- #----------------------------------------
...@@ -237,7 +236,6 @@ TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY; ...@@ -237,7 +236,6 @@ TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#---------------------------------------- #----------------------------------------
# Asynchronous resets # Asynchronous resets
#---------------------------------------- #----------------------------------------
# GN4124 # GN4124
NET "gn_rst_n_i" TIG; NET "gn_rst_n_i" TIG;
...@@ -247,11 +245,10 @@ NET "*/gc_reset_async_in" TIG; ...@@ -247,11 +245,10 @@ NET "*/gc_reset_async_in" TIG;
#---------------------------------------- #----------------------------------------
# Cross-clock domain sync # Cross-clock domain sync
#---------------------------------------- #----------------------------------------
# Declaration of domains # Declaration of domains
NET "cmp_spec_template_wr/clk_sys_62m5" TNM_NET = sys_clk_62_5; NET "cmp_spec_template_wr/clk_sys_62m5" TNM_NET = sys_clk_62_5;
NET "cmp_spec_template_wr/clk_ref_125m" TNM_NET = clk_125m_pllref; NET "cmp_spec_template_wr/clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "cmp_spec_template_wr/clk_ddr_333m" TNM_NET = ddr_clk_333m; NET "cmp_spec_template_wr/clk_ddr_333m" TNM_NET = ddr_clk;
NET "*cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd; NET "*cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk; NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk; NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
...@@ -283,17 +280,17 @@ TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk"; ...@@ -283,17 +280,17 @@ TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY; TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY; TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5 TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY; TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY; #TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY; TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_wr (3x multicycle) # Exceptions for crossings via gc_sync_word_wr (3x multicycle)
NET "*/gc_sync_word_wr_data[*]" TNM = FFS "sync_word"; NET "*/gc_sync_word_wr_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY; #TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
TIMESPEC TS_sys_62m5_sync_word = FROM sync_word TO sys_clk_62_5 48ns DATAPATHONLY; TIMESPEC TS_sys_62m5_sync_word = FROM sync_word TO sys_clk_62_5 48ns DATAPATHONLY;
TIMESPEC TS_sys_125m_sync_word = FROM sync_word TO clk_125m_pllref 24ns DATAPATHONLY; TIMESPEC TS_sys_125m_sync_word = FROM sync_word TO clk_125m_pllref 24ns DATAPATHONLY;
TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY; #TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
TIMESPEC TS_phy_sync_word = FROM sync_word TO phy_clk 24ns DATAPATHONLY; #TIMESPEC TS_phy_sync_word = FROM sync_word TO phy_clk 24ns DATAPATHONLY;
# DDR (bank 3) # DDR (bank 3)
NET "ddr0_rzq_b" LOC = K7; NET "ddr0_rzq_b" LOC = K7;
...@@ -467,7 +464,6 @@ NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25"; ...@@ -467,7 +464,6 @@ NET "fmc0_adc_one_wire_b" IOSTANDARD = "LVCMOS25";
#---------------------------------------- #----------------------------------------
# IOBs # IOBs
#---------------------------------------- #----------------------------------------
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE; INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE; INST "cmp0_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE; INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
...@@ -475,25 +471,21 @@ INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FA ...@@ -475,25 +471,21 @@ INST "cmp0_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FA
#---------------------------------------- #----------------------------------------
# Clocks # Clocks
#---------------------------------------- #----------------------------------------
NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i; NET "fmc0_adc_dco_n_i" TNM_NET = fmc0_adc_dco_n_i;
TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%; TIMESPEC TS_fmc0_adc_dco_n_i = PERIOD "fmc0_adc_dco_n_i" 2.5 ns HIGH 50%;
#---------------------------------------- #----------------------------------------
# Xilinx MCB tweaks # Xilinx MCB tweaks
#---------------------------------------- #----------------------------------------
# These are suggested by the Xilinx-generated MCB. # These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core. # More info in the UCF file found in the "user_design/par" of the generated core.
NET "*cmp_ddr_ctrl_bank3/*/c?_pll_lock" TIG; NET "*cmp_ddr_ctrl_bank3/*/c?_pll_lock" TIG;
NET "*cmp_ddr_ctrl_bank3/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG; NET "*cmp_ddr_ctrl_bank3/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "*cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG; NET "*cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#ERR NET "*cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG; #ERR NET "*cmp_ddr_ctrl_bank3/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#---------------------------------------- #----------------------------------------
# Asynchronous resets # Asynchronous resets
#---------------------------------------- #----------------------------------------
# Ignore async reset to DDR controller # Ignore async reset to DDR controller
NET "cmp_spec_template_wr/ddr_rst" TPTHRU = ddr_rst; NET "cmp_spec_template_wr/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG; TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
...@@ -501,27 +493,24 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG; ...@@ -501,27 +493,24 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#---------------------------------------- #----------------------------------------
# Cross-clock domain sync # Cross-clock domain sync
#---------------------------------------- #----------------------------------------
NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk; NET "cmp0_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/fs_clk" TNM_NET = fs_clk;
NET "*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr0_bank3_clk; NET "*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
TIMEGRP "ddr0_clk" = "ddr0_clk_333m" "ddr0_bank3_clk";
TIMEGRP "ddr0_sync_ffs" = "sync_ffs" EXCEPT "ddr0_clk"; #TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
TIMEGRP "fmc0_adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk"; TIMEGRP "fmc_adc_sync_ffs" = "sync_ffs" EXCEPT "fs_clk";
TIMESPEC TS_ddr0_sync_ffs = FROM ddr0_clk TO "ddr0_sync_ffs" TIG; #TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
TIMESPEC TS_adc0_sync_ffs = FROM fs0_clk TO "adc0_sync_ffs" TIG; TIMESPEC TS_adc_sync_ffs = FROM fs_clk TO "fmc_adc_sync_ffs" TIG;
TIMEGRP "ddr0_sync_reg" = "sync_reg" EXCEPT "ddr0_clk"; #TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
TIMEGRP "fmc0_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk"; TIMEGRP "fmc_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY; #TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc0_adc_sync_reg" 10ns DATAPATHONLY; TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc_adc_sync_reg" 10ns DATAPATHONLY;
TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY; #TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 40ns DATAPATHONLY; TIMESPEC TS_adc_sync_word = FROM sync_word TO fs_clk 30ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input # Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger # to its synchroniser. This is needed to have consistent alignment between trigger
......
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