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White Rabbit Trigger Distribution
Commits
7bc611e3
Commit
7bc611e3
authored
Sep 25, 2019
by
Dimitris Lampridis
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[hdl] use SPEC v1.4.1
parent
a591946f
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3 changed files
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7 additions
and
7 deletions
+7
-7
spec
dependencies/spec
+1
-1
dut_env.sv
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
+4
-4
main.sv
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
+2
-2
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spec
@
e52fec7c
Subproject commit
1b48d76430920f62e871ce0e46bc61731f04d9b1
Subproject commit
e52fec7c961efbc3f66419fc8eb2d16accef0e2a
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @
7bc611e3
...
...
@@ -288,16 +288,16 @@ module dut_env
initial
begin
// Skip WR SoftPLL lock
force
DUT
.
inst_spec_
templat
e
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
inst_spec_
bas
e
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
U_SOFTPLL
.
U_Wrapped_Softpll
.
out_locked_o
=
3'b111
;
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force
DUT
.
inst_spec_
templat
e
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
inst_spec_
bas
e
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D1
.
OPMODE_dly
=
0
;
force
DUT
.
inst_spec_
templat
e
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
inst_spec_
bas
e
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D2
.
OPMODE_dly
=
0
;
force
DUT
.
inst_spec_
templat
e
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
force
DUT
.
inst_spec_
bas
e
.
gen_wr
.
cmp_xwrc_board_spec
.
cmp_board_common
.
cmp_xwr_core
.
WRPC
.
LM32_CORE
.
gen_profile_medium_icache
.
U_Wrapped_LM32
.
cpu
.
multiplier
.
D3
.
OPMODE_dly
=
0
;
end
// initial begin
...
...
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @
7bc611e3
...
...
@@ -181,7 +181,7 @@ module main;
accA
.
write
(
`DMA_BASE
+
'h00
,
'h00000001
)
;
// xfer start
wait
(
DUTA
.
DUT
.
inst_spec_
templat
e
.
irqs
[
2
]
==
1
)
;
wait
(
DUTA
.
DUT
.
inst_spec_
bas
e
.
irqs
[
2
]
==
1
)
;
$
display
(
"[DUT:A] <%t> END DMA 1"
,
$
realtime
)
;
accA
.
write
(
`DMA_BASE
+
'h04
,
'h04
)
;
// clear DMA IRQ
accA
.
write
(
`VIC_BASE
+
'h1c
,
'h0
)
;
...
...
@@ -211,7 +211,7 @@ module main;
accB
.
write
(
`DMA_BASE
+
'h00
,
'h00000001
)
;
// xfer start
wait
(
DUTB
.
DUT
.
inst_spec_
templat
e
.
irqs
[
2
]
==
1
)
;
wait
(
DUTB
.
DUT
.
inst_spec_
bas
e
.
irqs
[
2
]
==
1
)
;
$
display
(
"[DUT:B] <%t> END DMA 1"
,
$
realtime
)
;
accB
.
write
(
`DMA_BASE
+
'h04
,
'h04
)
;
// clear DMA IRQ
accB
.
write
(
`VIC_BASE
+
'h1c
,
'h0
)
;
...
...
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