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White Rabbit Trigger Distribution
Commit 832aa28e authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: update and tighten top-level constraints for SPEC150T-ADC ref design

parent e983c94f
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Showing with 12 additions and 5 deletions
general-cores @ 28cd7560
Subproject commit 67d353adecea74d6a29e21919ff714da94fd8c76 Subproject commit 28cd756047ce9f85cf7c134367c7439f1189114d
hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
View file @ 832aa28e
...@@ -264,7 +264,7 @@ TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref"; ...@@ -264,7 +264,7 @@ TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk"; TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk";
# Exceptions for crossings via gc_sync_ffs # Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs"; NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk"; TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk"; TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
...@@ -277,7 +277,7 @@ TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG; ...@@ -277,7 +277,7 @@ TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG; TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register # Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg"; NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk"; TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk"; TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
...@@ -513,3 +513,10 @@ TIMEGRP "fmc0_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk"; ...@@ -513,3 +513,10 @@ TIMEGRP "fmc0_adc_sync_reg" = "sync_reg" EXCEPT "fs_clk";
TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY; TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr0_sync_reg" 3ns DATAPATHONLY;
TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc0_adc_sync_reg" 10ns DATAPATHONLY; TIMESPEC TS_adc_sync_reg = FROM fs_clk TO "fmc0_adc_sync_reg" 10ns DATAPATHONLY;
# Tightly constrain the location and max delay from the external trigger input
# to its synchroniser. This is needed to have consistent alignment between trigger
# and data across implementations. Note that due to RLOC constraints in the
# gc_sync_ffs, the synchroniser cannot be placed on the single FF of the IOB.
NET "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
INST "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X68Y2;
hdl/top/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.vhd
View file @ 832aa28e
...@@ -936,8 +936,8 @@ begin -- architecture arch ...@@ -936,8 +936,8 @@ begin -- architecture arch
g_MULTISHOT_RAM_SIZE => g_FMC0_MULTISHOT_RAM_SIZE, g_MULTISHOT_RAM_SIZE => g_FMC0_MULTISHOT_RAM_SIZE,
g_SPARTAN6_USE_PLL => FALSE, g_SPARTAN6_USE_PLL => FALSE,
g_TRIG_DELAY_EXT => 7, g_TRIG_DELAY_EXT => 7,
g_TRIG_DELAY_SW => 9, g_TRIG_DELAY_SW => 10,
g_TAG_ADJUST => 24, g_TAG_ADJUST => 26,
g_WB_MODE => PIPELINED, g_WB_MODE => PIPELINED,
g_WB_GRANULARITY => BYTE) g_WB_GRANULARITY => BYTE)
port map ( port map (
......
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