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White Rabbit Trigger Distribution
Commit 86d87a5a authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] bump gn4124 core to bring in dma controller IRQ status fix and make SPEC… 

[hdl] bump gn4124 core to bring in dma controller IRQ status fix and make SPEC testbench work with interrupts
parent 19fa3271
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Showing with 50 additions and 31 deletions
general-cores @ 116a9bf8
Subproject commit 14e96565da18eee7960c69f927edc31e820a2e3c
Subproject commit 116a9bf84354b82265b21f34a918342ca583bb4e
gn4124-core @ 3159ffcd
Subproject commit d46281e65b39f1c3fe25686b3d14dadbc854438f
Subproject commit 3159ffcd833bd1308c6d2fe592ad58f000368d62
hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
View file @ 86d87a5a
......@@ -15,7 +15,7 @@ sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware"
include_dirs = [
"../include",
fetchto + "/gn4124-core/hdl/gn4124core/sim/gn4124_bfm",
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim",
fetchto + "/mock-turtle/hdl/testbench/include",
fetchto + "/fmc-adc-100m14b4cha-gw/hdl/testbench/include",
......
hdl/testbench/wrtd_ref_spec150t_adc/dut_env.sv
View file @ 86d87a5a
......@@ -30,7 +30,6 @@
module dut_env
(
IGN4124PCIMaster i_gn4124,
output[2:0] acq_fsm_state,
output sfp_txp_o, sfp_txn_o,
input sfp_rxp_i, sfp_rxn_i,
input ext_trigger_i
......@@ -187,8 +186,6 @@ module dut_env
.fmc0_sda_b ()
);
assign acq_fsm_state = DUT.cmp0_fmc_adc_mezzanine.cmp_fmc_adc_100Ms_core.acq_fsm_state;
//---------------------------------------------------------------------------
// DDR memory model
//---------------------------------------------------------------------------
......
hdl/testbench/wrtd_ref_spec150t_adc/main.sv
View file @ 86d87a5a
......@@ -30,7 +30,10 @@
`include "fmc_adc_100Ms_csr.v"
`include "fmc_adc_alt_trigout.v"
`define DMA_BASE 'h00c0
`define VIC_BASE 'h0100
`define ADC_CSR_BASE 'h5000
`define ADC_EIC_BASE 'h5500
module main;
......@@ -38,10 +41,9 @@ module main;
IGN4124PCIMaster hostB ();
reg duta_ext_trig, dutb_ext_trig;
wire[2:0] duta_acq_state, dutb_acq_state;
dut_env DUTA (hostA, duta_acq_state, a2b_txp, a2b_txn, a2b_rxp, a2b_rxn, duta_ext_trig);
dut_env DUTB (hostB, dutb_acq_state, a2b_rxp, a2b_rxn, a2b_txp, a2b_txn, dutb_ext_trig);
dut_env DUTA (hostA, a2b_txp, a2b_txn, a2b_rxp, a2b_rxn, duta_ext_trig);
dut_env DUTB (hostB, a2b_rxp, a2b_rxn, a2b_txp, a2b_txn, dutb_ext_trig);
IMockTurtleIRQ MtIrqMonitorA (`MT_ATTACH_IRQ(DUTA.DUT.cmp_mock_turtle));
IMockTurtleIRQ MtIrqMonitorB (`MT_ATTACH_IRQ(DUTB.DUT.cmp_mock_turtle));
......@@ -72,6 +74,13 @@ module main;
devA.set_rule ( "rule0", "LC-I5", "NET0", 0 );
devA.enable_rule ( "rule0" );
// Configure the EIC for an interrupt on ACQ_END
accA.write(`ADC_EIC_BASE + 'h4, 'h2);
// Configure the VIC
accA.write(`VIC_BASE + 'h8, 'h7f);
accA.write(`VIC_BASE + 'h0, 'h1);
// Config DUTA to trigger on external trigger and get 64 samples
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00);
accA.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40);
......@@ -95,7 +104,6 @@ module main;
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
$display ("[DUT:A] <%t> ADC configured and armed", $realtime);
wait (duta_acq_state == 1);
end
begin
......@@ -107,6 +115,13 @@ module main;
devB.set_rule ( "rule0", "NET0", "LC-O1", 50000 );
devB.enable_rule ( "rule0" );
// Configure the EIC for an interrupt on ACQ_END
accB.write(`ADC_EIC_BASE + 'h4, 'h2);
// Configure the VIC
accB.write(`VIC_BASE + 'h8, 'h7f);
accB.write(`VIC_BASE + 'h0, 'h1);
// Config DUTB to trigger on WRTD and get 64 samples
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00);
accB.write(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h40);
......@@ -129,7 +144,6 @@ module main;
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
$display ("[DUT:B] <%t> ADC configured and armed", $realtime);
wait (dutb_acq_state == 1);
end
join
......@@ -147,55 +161,63 @@ module main;
fork
begin
wait (duta_acq_state == 1);
wait (DUTA.DUT.cmp0_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("[DUT:A] <%t> END ACQ 1", $realtime);
accA.write(`ADC_EIC_BASE + 'hc, 'h2);
accA.write(`VIC_BASE + 'h1c, 'h0);
accA.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("[DUT:A] <%t> TRIG POSITION %.8x", $realtime, val);
// DMA transfer
accA.write('h2008, val); // dma start addr
accA.write(`DMA_BASE + 'h08, val); // dma start addr
accA.write('h200C, 'h00001000); // host addr
accA.write('h2010, 'h00000000);
accA.write(`DMA_BASE + 'h0C, 'h00001000); // host addr
accA.write(`DMA_BASE + 'h10, 'h00000000);
accA.write('h2014, 'h00000100); // len << 2
accA.write(`DMA_BASE + 'h14, 'h00000100); // len << 2
accA.write('h2018, 'h00000000); // next
accA.write('h201C, 'h00000000);
accA.write(`DMA_BASE + 'h18, 'h00000000); // next
accA.write(`DMA_BASE + 'h1C, 'h00000000);
accA.write('h2020, 'h00000000); // attrib: pcie -> host
accA.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
accA.write('h2000, 'h00000001); // xfer start
accA.write(`DMA_BASE + 'h00, 'h00000001); // xfer start
wait (DUTA.DUT.inst_spec_template.irqs[0] == 1);
wait (DUTA.DUT.inst_spec_template.irqs[2] == 1);
$display("[DUT:A] <%t> END DMA 1", $realtime);
accA.write(`DMA_BASE + 'h04, 'h04); // clear DMA IRQ
accA.write(`VIC_BASE + 'h1c, 'h0);
end
begin
wait (dutb_acq_state == 1);
wait (DUTB.DUT.cmp0_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("[DUT:B] <%t> END ACQ 1", $realtime);
accB.write(`ADC_EIC_BASE + 'hc, 'h2);
accB.write(`VIC_BASE + 'h1c, 'h0);
accB.read(`ADC_CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("[DUT:B] <%t> TRIG POSITION %.8x", $realtime, val);
// DMA transfer
accB.write('h2008, val); // dma start addr
accB.write(`DMA_BASE + 'h08, val); // dma start addr
accB.write('h200C, 'h00001000); // host addr
accB.write('h2010, 'h00000000);
accB.write(`DMA_BASE + 'h0C, 'h00001000); // host addr
accB.write(`DMA_BASE + 'h10, 'h00000000);
accB.write('h2014, 'h00000100); // len << 2
accB.write(`DMA_BASE + 'h14, 'h00000100); // len << 2
accB.write('h2018, 'h00000000); // next
accB.write('h201C, 'h00000000);
accB.write(`DMA_BASE + 'h18, 'h00000000); // next
accB.write(`DMA_BASE + 'h1C, 'h00000000);
accB.write('h2020, 'h00000000); // attrib: pcie -> host
accB.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
accB.write('h2000, 'h00000001); // xfer start
accB.write(`DMA_BASE + 'h00, 'h00000001); // xfer start
wait (DUTB.DUT.inst_spec_template.irqs[0] == 1);
wait (DUTB.DUT.inst_spec_template.irqs[2] == 1);
$display("[DUT:B] <%t> END DMA 1", $realtime);
accB.write(`DMA_BASE + 'h04, 'h04); // clear DMA IRQ
accB.write(`VIC_BASE + 'h1c, 'h0);
end
join
......
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