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White Rabbit Trigger Distribution
Commit 895916a8 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: update timing constraints for svec/list_tdc_fd project

parent eb448f2e
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Showing with 19 additions and 22 deletions
general-cores @ 01731cd1
Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
Subproject commit 01731cd1675402d6b2a8139ec7c8ad9bf64a3507
mock-turtle @ 5ce1aa6d
Subproject commit e798aa45e70d55165e5dda4d3dbd09ea426c3fc7
Subproject commit 5ce1aa6d129d8262c2fca4b488f07d4edfc0b428
hdl/syn/svec/list_tdc_fd/Manifest.py
View file @ 895916a8
......@@ -14,6 +14,10 @@ syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE)"
files = [
"svec_list_top.ucf",
]
modules = {
"local" : [
"../../../top/svec/list_tdc_fd",
......
hdl/top/svec/list_tdc_fd/svec_list_top.ucf → hdl/syn/svec/list_tdc_fd/svec_list_top.ucf
View file @ 895916a8
......@@ -701,35 +701,28 @@ TIMESPEC TS_fmc0_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_125m_clk_n_i" 8 ns HIGH 50%
NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
# relax all paths through syncrhonisers
NET "clk_ref_125m" TNM_NET = clk_125m_pllref;
NET "clk_sys_62m5" TNM_NET = clk_sys;
NET "dcm1_clk_ref_0" TNM_NET = dcm1_clk_ref_0;
NET "tdc_clk_125m" TNM_NET = tdc_clk_125m;
NET "cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_rx_rbclk;
TIMESPEC TS_crossdomain_1 = FROM "clk_sys" TO "clk_125m_pllref" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_2 = FROM "clk_125m_pllref" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_3 = FROM "clk_sys" TO "phy_rx_rbclk" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_4 = FROM "phy_rx_rbclk" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_5 = FROM "clk_125m_pllref" TO "phy_rx_rbclk" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_6 = FROM "phy_rx_rbclk" TO "clk_125m_pllref" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_7 = FROM "clk_sys" TO "tdc_clk_125m" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_8 = FROM "tdc_clk_125m" TO "clk_sys" 20ns DATAPATHONLY;
NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
TIMESPEC TS_crossdomain_9 = FROM "clk_sys" TO "dcm1_clk_ref_0" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_10 = FROM "dcm1_clk_ref_0" TO "clk_sys" 20ns DATAPATHONLY;
TIMEGRP "synchronizers"="sync_ffs" "sync_reg";
TIMESPEC TS_crossdomain_11 = FROM "clk_125m_pllref" TO "dcm1_clk_ref_0" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_12 = FROM "dcm1_clk_ref_0" TO "clk_125m_pllref" 20ns DATAPATHONLY;
TIMESPEC TS_ref_sync_ffs = FROM clk_125m_pllref TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_ffs = FROM clk_sys TO "synchronizers" 16ns DATAPATHONLY;
TIMESPEC TS_fdl_sync_ffs = FROM dcm1_clk_ref_0 TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_tdc_sync_ffs = FROM tdc_clk_125m TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_phy_sync_ffs = FROM phy_rx_rbclk TO "synchronizers" 8ns DATAPATHONLY;
TIMESPEC TS_crossdomain_13 = FROM "clk_125m_pllref" TO "tdc_clk_125m" 20ns DATAPATHONLY;
TIMESPEC TS_crossdomain_14 = FROM "tdc_clk_125m" TO "clk_125m_pllref" 20ns DATAPATHONLY;
# one more path where TAI time crosses from WR ref to MT sys clock
NET "cmp_mock_turtle/gen_cpus[*].U_CPU_Block/tm_p_sys" TNM_NET = "tm_mt_sync";
NET "*/gc_sync_register_in[*]" MAXDELAY=4ns;
TIMESPEC TS_tm_mt_sync = FROM clk_125m_pllref TO "tm_mt_sync" 16ns DATAPATHONLY;
# External async resets
NET "rst_n_i" TIG;
......
hdl/top/svec/list_tdc_fd/Manifest.py
View file @ 895916a8
files = [
"svec_list_top.vhd",
"svec_list_top.ucf",
]
fetchto = "../../../ip_cores"
......
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